公开(公告)号：US20160380190A1

公开(公告)日：2016-12-29

申请号：US15098025

申请日：2016-04-13

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Abstract translation: 存储单元包括具有控制栅极的选择晶体管和连接到可变电阻元件的第一导电端子。 存储单元形成在包括被第一绝缘层覆盖的半导体衬底的晶片中，绝缘层被由半导体制成的有源层覆盖。 栅极形成在有源层上，并具有用第二绝缘层覆盖的侧面。 可变电阻元件包括覆盖有源层的横向侧面的第一层，该沟槽沿着栅极的侧面通过有源层形成并且到达第一绝缘层的沟槽，以及由可变电阻材料制成的第二层 。

公开(公告)号：US09530686B1

公开(公告)日：2016-12-27

申请号：US15043830

申请日：2016-02-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Bidal

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0684 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

Abstract translation: MOS晶体管包括搁置在绝缘体上并具有基本平坦的上表面的半导体层。 半导体层在沟道区域中向下延伸到第一深度，并且在源极和漏极区域中向下延伸大于第一深度的第二深度。 在沟道区域中，半导体层由绝缘体上硅衬底的上半导体层的一部分形成。 在源区和漏区中，通过外延生长的半导体材料形成半导体层。

公开(公告)号：US20160372510A1

公开(公告)日：2016-12-22

申请号：US14960018

申请日：2015-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/1892 ,  H01L2224/05

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

Abstract translation: 电子部件包括具有涂覆有第一绝缘层的第一表面和涂覆有互连结构的第二表面的半导体层。 横向绝缘的导电针从互连结构的导电层的一部分延伸穿过半导体层到布置在第一绝缘层的层的接触焊盘。

公开(公告)号：US09525067B2

公开(公告)日：2016-12-20

申请号：US14533770

申请日：2014-11-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel-Camille Bensahel ,  Aomar Halimaoui

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/06 ,  H01L29/32 ,  H01L21/18 ,  H01L21/3063

CPC classification number: H01L29/7849 ,  H01L21/187 ,  H01L21/3063 ,  H01L29/06 ,  H01L29/32 ,  H01L29/78

Abstract: An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

Abstract translation: 应变半导体衬底上的电子电路包括：半导体衬底的第一表面上的电子部件; 以及半导体衬底的与第一表面相对的一侧上的多孔半导体材料层的至少一部分，以使半导体衬底弯曲。

公开(公告)号：US09523815B2

公开(公告)日：2016-12-20

申请号：US14638292

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Estelle Batail

IPC: G02B6/42 ,  G02B6/122 ,  H01L29/74 ,  H01L27/02

CPC classification number: G02B6/122 ,  G02B6/4275 ,  G02B6/4295 ,  H01L27/0248 ,  H01L29/74

Abstract: A thyristor may include a first optical waveguide segment in a semiconductor material, having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. The thyristor may further include a second optical waveguide segment in a semiconductor material, adjacent the first waveguide segment and having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. A transverse bipolar junction may be between the second longitudinal portions of the first and second waveguide segments. An electrical insulator may separate each of the first longitudinal portions from the waveguide segment adjacent thereto.

Abstract translation: 晶闸管可以包括半导体材料中的第一光波导段，其具有构造为在其间形成纵向双极结的相反导电类型的第一和第二互补纵向部分。 晶闸管可以进一步包括半导体材料中的第二光波导段，邻近第一波导段并且具有构造成在其间形成纵向双极结的相反导电类型的第一和第二互补纵向部分。 横向双极结可以在第一和第二波导段的第二纵向部分之间。 电绝缘体可以将每个第一纵向部分与与其相邻的波导段分开。

公开(公告)号：US09520435B2

公开(公告)日：2016-12-13

申请号：US14840665

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Nayera Ahmed ,  Michel Marty

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor including a semiconductor layer; a stack of insulating layers resting on the back side of the semiconductor layer; a conductive layer portion extending along part of the height of the stack and flush with the exposed surface of the stack; laterally-insulated conductive fingers extending through the semiconductor layer from its front side and penetrating into said layer portion; laterally-insulated conductive walls separating pixel areas, these walls extending through the semiconductor layer from its front side and having a lower height than the fingers; and an interconnection structure resting on the front side of the semiconductor layer and including vias in contact with the fingers.

Abstract translation: 包括半导体层的图像传感器; 沉积在半导体层的背面上的一叠绝缘层; 导电层部分，其沿所述堆叠的高度的一部分延伸并与所述堆叠的暴露表面齐平; 横向绝缘的导电指状物从其前侧延伸穿过半导体层并且穿透到所述层部分中; 分隔像素区域的横向绝缘导电壁，这些壁从其前侧延伸穿过半导体层并且具有比手指低的高度; 以及搁置在半导体层的前侧上并且包括与手指接触的通孔的互连结构。

公开(公告)号：US09502558B2

公开(公告)日：2016-11-22

申请号：US14791713

申请日：2015-07-06

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Shay Reboh ,  Laurent Grenouillet ,  Cyrille Le Royer ,  Sylvain Maitrejean ,  Yves Morand

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26506 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/7849

Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.

Abstract translation: 使用在晶体管栅极制造之前利用其中位于衬底（图6）的绝缘层下方的区域非晶化的SMT应力存储技术的半导体绝缘体型晶体管的晶体管的沟道区域的方法 。

公开(公告)号：US09437694B1

公开(公告)日：2016-09-06

申请号：US14676369

申请日：2015-04-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Clement Gaumer ,  Daniel Benoit

IPC: H01L21/8232 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/41783 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/78

Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

Abstract translation: 通过在半导体层的顶部上限定栅极叠层来形成晶体管。 栅极堆叠包括栅极电介质和栅电极。 具有第一介电常数的第一介电材料层沉积在栅极堆叠的侧壁上以形成牺牲侧壁间隔物。 然后在邻近牺牲侧壁间隔物的栅极堆叠的每一侧外延生长凸起的源极 - 漏极区域。 然后去除牺牲侧壁间隔物，以在每个凸起的源极 - 漏极区域和栅极堆叠之间产生开口。 然后将具有小于第一介电常数的第二介电常数的第二介电材料层沉积在栅极堆叠的开口和侧壁中以形成低k侧壁间隔物。

公开(公告)号：US09437498B2

公开(公告)日：2016-09-06

申请号：US14636778

申请日：2015-03-03

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Stéphane Zoll ,  Philippe Garnier ,  Olivier Gourhant ,  Vincent Joseph

IPC: H01L21/3205 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/324 ,  H01L21/033 ,  H01L21/28

CPC classification number: H01L21/823437 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/324 ,  H01L29/4966

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract translation: 一种方法是形成至少两个MOS晶体管的至少两个不同的栅极金属区域。 该方法可以包括在栅介质层上形成金属层; 以及在所述金属层上形成金属硬掩模，所述硬掩模具有不同于所述金属层的组成，并且覆盖所述金属层的第一区域并且留下所述金属层的第二区域。 该方法还可以包括对先前步骤中获得的中间结构进行扩散退火，以使硬掩模的金属原子扩散到第一区域中，以及去除硬掩模。

公开(公告)号：US09418954B2

公开(公告)日：2016-08-16

申请号：US14659680

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/3213 ,  H01L21/56 ,  H01L21/768 ,  H01L23/36 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract translation: 一种装置包括组装在插入器上的芯片。 电绝缘层在芯片周围涂覆插入件的上表面。 第一金属线在插入件的上表面上延伸并且布置在与芯片连接的导电元件之间。 每个第一金属线的端部被布置成延伸超过芯片在插入件上的投影。 导热通孔将第一金属线的端部连接到支撑在设备的上表面处的散热器。