公开(公告)号：US20120091580A1

公开(公告)日：2012-04-19

申请号：US13211574

申请日：2011-08-17

Applicant: SeYoung Jeong ,  Hogeon Song ,  Chungsun Lee ,  Ho-Jin Lee

Inventor： SeYoung Jeong ,  Hogeon Song ,  Chungsun Lee ,  Ho-Jin Lee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is a semiconductor device. The semiconductor device may include a first semiconductor chip that includes a first through silicon via having a first protrusion height and a second through silicon via having a second protrusion height greater than the first protrusion height which are penetrating at least a portion of the first semiconductor chip, a second semiconductor chip may be electrically connected to the first through silicon via, and a third semiconductor chip may be electrically connected to the second through silicon via.

Abstract translation: 提供一种半导体器件。 半导体器件可以包括第一半导体芯片，其包括具有第一突起高度的第一至第二硅通孔以及具有大于第一突出高度的第二突出高度的第二穿透硅通孔，该第二突出高度穿过第一半导体芯片的至少一部分 ，第二半导体芯片可以电连接到第一通孔硅通孔，并且第三半导体芯片可以电连接到第二通孔硅通孔。

公开(公告)号：US20120049349A1

公开(公告)日：2012-03-01

申请号：US13178156

申请日：2011-07-07

Applicant: Ho-Jin LEE ,  Donghyeon JANG ,  Hogeon SONG ,  SeYoung JEONG ,  Minseung YOON ,  Jung-Hwan KIM

Inventor： Ho-Jin LEE ,  Donghyeon JANG ,  Hogeon SONG ,  SeYoung JEONG ,  Minseung YOON ,  Jung-Hwan KIM

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L21/76898

Abstract: Provided is a semiconductor chip including a back side insulation structure. The semiconductor chip may include a semiconductor layer including an active surface and an inactive surface facing each other; the insulating layer includes a first surface adjacent to the inactive surface and a second surface facing the first surface. The insulating layer is disposed on the inactive surface of the semiconductor layer. A penetrating electrode fills a hole penetrating the semiconductor layer and the insulating layer. The through electrode comprises a protrusive portion protruding from the second surface of the insulating layer.

Abstract translation: 提供了包括背面绝缘结构的半导体芯片。 半导体芯片可以包括半导体层，其包括相互面对的有源表面和非活性表面; 绝缘层包括与非活性表面相邻的第一表面和面向第一表面的第二表面。 绝缘层设置在半导体层的非活性表面上。 穿透电极填充穿透半导体层和绝缘层的孔。 贯通电极包括从绝缘层的第二表面突出的突出部分。

公开(公告)号：US08120177B2

公开(公告)日：2012-02-21

申请号：US12910260

申请日：2010-10-22

Applicant: Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

Abstract: In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

公开(公告)号：US20110284936A1

公开(公告)日：2011-11-24

申请号：US13108231

申请日：2011-05-16

Applicant: Ju-il CHOI ,  Jae-hyun Phee ,  Hyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

Inventor： Ju-il CHOI ,  Jae-hyun Phee ,  Hyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC: H01L29/772 ,  H01L23/48

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。

公开(公告)号：US08049319B2

公开(公告)日：2011-11-01

申请号：US12604354

申请日：2009-10-22

Applicant: In-Kwon Ju ,  In-Bok Yom ,  Ho-Jin Lee

Inventor： In-Kwon Ju ,  In-Bok Yom ,  Ho-Jin Lee

IPC: H01L23/02 ,  H01L23/053 ,  H01L23/12 ,  H01L23/34

CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1423 ,  H01L2924/19032 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.

Abstract translation: 该研究公开了一种超宽带系统级封装（SoP）。 SoP包括一个包装体; 安装在封装主体上的第一集成电路; 连接到第一集成电路的第一信号传输单元; 连接到第一信号传输单元并包括板条线和槽线的信号通路; 以及连接到信号通道的第二信号传输单元。 本研究的技术可以通过最小化在向外部电路传输信号的过程中发生的垂直转换期间出现的信号的不连续性来传输超宽带信号及其制造方法。

公开(公告)号：US07995578B2

公开(公告)日：2011-08-09

申请号：US12334043

申请日：2008-12-12

Applicant: Pansoo Kim ,  In-Ki Lee ,  Dae-Ig Chang ,  Ho-Jin Lee ,  Namshik Kim ,  Bongseop Song ,  Hyuncheol Park

Inventor： Pansoo Kim ,  In-Ki Lee ,  Dae-Ig Chang ,  Ho-Jin Lee ,  Namshik Kim ,  Bongseop Song ,  Hyuncheol Park

IPC: H04J3/16

CPC classification number: H04L1/0071 ,  H04L1/0013 ,  H04L1/0068 ,  H04L1/08

Abstract: Provided are repetition apparatus and method for repeatedly transmitting and receiving a data packet using different puncturing patterns to overcome signal attenuation and fading in a high speed mobile environment by repeatedly transmitting the duplicated information bit sequences with parity bits having a different puncturing pattern after channel-encoding the duplicated information bit. The repetition apparatus for repeatedly transmitting a data packet, includes a dual data generator for generating duplicated information bit sequences identical to each of information bit sequences to transmit, a channel encoder for dividing each of the duplicated information bit sequences into a plurality of information bits, and generating coded data packets alternately having a plurality of parity bits according to different puncturing patterns for each of the divided information bits, and a transmitter for transmitting the generated coded data packets sequentially.

Abstract translation: 提供了一种重复装置和方法，用于使用不同的打孔模式重复地发送和接收数据包，以通过在频道编码之后重复地发送具有不同打孔图案的奇偶校验位的复制信息比特序列来克服高速移动环境中的信号衰减和衰落 重复的信息位。 用于重复发送数据分组的重复装置包括：双数据产生器，用于产生与要发送的每个信息比特序列相同的重复信息比特序列，用于将每个复制信息比特序列分成多个信息比特的信道编码器， 以及根据用于每个分割的信息比特的不同的删截图案，交替地生成具有多个奇偶校验位的编码数据分组，以及发送器，用于顺序地发送所生成的编码数据分组。

公开(公告)号：US20110151777A1

公开(公告)日：2011-06-23

申请号：US12973517

申请日：2010-12-20

Applicant: Pan Soo KIM ,  Jae Hee Han ,  Dae Ig Chang ,  Ho Jin Lee

Inventor： Pan Soo KIM ,  Jae Hee Han ,  Dae Ig Chang ,  Ho Jin Lee

IPC: H04B7/185 ,  H04W52/04

CPC classification number: H04B7/18528

Abstract: Provided are a satellite VSAT apparatus and a control method thereof. The satellite VSAT apparatus according to an exemplary embodiment of the present invention can switch a modulation type of a signal to be transmitted from an indoor unit (IDU) to the outdoor unit to a linear or non-linear type in a case in which outputting of a transmitted signal is not controlled to an outdoor unit due to limitations, that is, there is no function such as an automatic signal level control in a block up-converter (BUC), a case in which transmission output limitation is large due to a lot of interference requirements for an adjacent channel, a case in which the number of adjacent channels (carriers) is large, or a case in which adjacent channel interference is large due to a frequency in a satellite multi-beam environment and polarization reuse, in a satellite VSAT apparatus system which aims at a low-priced user terminal.

Abstract translation: 提供了一种卫星VSAT装置及其控制方法。 在根据本发明的示例性实施例的卫星VSAT装置可以将输出从室内单元（IDU）到室外单元的信号的调制类型切换到线性或非线性类型， 发送信号由于限制而不被控制到室外机，也就是说，在块升压转换器（BUC）中不存在诸如自动信号电平控制的功能，由于发送信号的发送输出限制大 相邻信道的大量干扰要求，相邻信道（载波）数量大的情况，或由于卫星多波束环境中的频率和极化重用而导致相邻信道干扰较大的情况，在 卫星VSAT装置系统，其目的在于低价格的用户终端。

公开(公告)号：US20110147946A1

公开(公告)日：2011-06-23

申请号：US13027594

申请日：2011-02-15

Applicant: In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

Inventor： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。

公开(公告)号：US20110091100A1

公开(公告)日：2011-04-21

申请号：US12805864

申请日：2010-08-20

Applicant: Ho Jin LEE ,  Young Su MOON ,  Shi Hwa LEE

Inventor： Ho Jin LEE ,  Young Su MOON ,  Shi Hwa LEE

IPC: G06K9/00

CPC classification number: H04N1/58 ,  G06T5/003 ,  G06T5/20 ,  G06T2207/10024 ,  G06T2207/20012 ,  G06T2207/20032

Abstract: An image processing method and apparatus is provided, with which a size of a filter window may be decreased by determining an edge direction of each of the pixels constituting an image and by vertically applying an anisotropic filter window to the determined edge direction.

Abstract translation: 提供了一种图像处理方法和装置，通过确定构成图像的每个像素的边缘方向以及通过垂直向所确定的边缘方向施加各向异性滤光器窗口，可以减小滤光器窗口的尺寸。

公开(公告)号：US20110086486A1

公开(公告)日：2011-04-14

申请号：US12969977

申请日：2010-12-16

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。