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    "> Integrated circuit interconnect structure with back reflection suppressing electronic
    63.
    发明授权
    Integrated circuit interconnect structure with back reflection suppressing electronic "speed bumps" 失效
    集成电路互连结构，具有背反射抑制电子“速度凸块”

    公开(公告)号：US5567988A

    公开(公告)日：1996-10-22

    申请号：US483113

    申请日：1995-06-07

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch

    IPC分类号： H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/522 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

    摘要翻译： 在微电子电路基板上形成多晶硅互连，用于传导来自驱动器的信号到具有比互连更高的阻抗的非多晶硅接触。 多个电子“速度凸块”沿着互连线间隔开，用于干扰或扰乱沿着互连向接触传播的信号，从而减少不期望的背反射和振铃。 速度凸块可以包括介质条形式的电容改变元件，或电阻变化元件，其形式为低电阻掺杂区域或高电阻无定形区域。 速度凸块可以包括具有不同的电容值或电阻值的第一和第二元件，这些元件沿着互连交替关系间隔开。

    Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation
    64.
    发明授权
    Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation 失效
    从较高级别创建和验证电子设计的低级结构描述的方法和系统，面向行为的描述，包括估计物理实现的功耗

    公开(公告)号：US5557531A

    公开(公告)日：1996-09-17

    申请号：US76738

    申请日：1993-06-14

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F11/26 ,  G06F17/50

    CPC分类号： G01R31/31704 ,  G01R31/318357 ,  G01R31/318364 ,  G01R31/318378 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045

    摘要： A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.Techniques are described for estimating the power and area requirements of the physical implementation of the device, at early, high level stages of the design process (e.g., at the system, behavioral, and register transfer level stages). The techniques are suited to the design of any semiconductor device, particularly CMOS devices.

    摘要翻译： 公开了一种用于从高级描述和规范生成复杂数字设备的结构描述的方法。 该方法使用系统的技术来绘制和实施嵌入原始高级描述意图的语义的一致性。 设计活动本质上是在各种级别的设计表示上运行的一系列变革。 在每个级别，捕获意图（语义）和正式的软件操作，以得到更详细的级别，描述符合设计目标的硬件。 方法的重要特征是：捕获用户的概念，意图，规范，描述，约束和权衡; 建筑分区; 高级别的假设分析; 尺寸估算; 定时估计; 建筑权衡; 概念设计与实施估计; 和时间关闭。 该方法包括使用估计器，基于在多个实现的设计上收集的数据，用于在逻辑综合之前对设计进行分区和评估。 从结构描述中，容易实现设备的物理实现。 描述了用于在设计过程的早期，高级阶段（例如，在系统，行为和寄存器传送级别阶段）处估计设备的物理实现的功率和面积要求的技术。 这些技术适用于任何半导体器件，特别是CMOS器件的设计。

    Molding compounds having a controlled thermal coefficient of expansion, and their uses in packaging electronic devices
    65.
    发明授权
    Molding compounds having a controlled thermal coefficient of expansion, and their uses in packaging electronic devices 失效
    具有受控的热膨胀系数的成型化合物及其在包装电子器件中的用途

    公开(公告)号：US5557066A

    公开(公告)日：1996-09-17

    申请号：US493956

    申请日：1995-06-23

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： H01L23/29 ,  H01L23/31 ,  H01L23/495 ,  H01J5/00

    CPC分类号： H01L23/3135 ,  H01L23/295 ,  H01L23/49558 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181

    摘要： Plastic (or resinous) materials used to package (or support) electronic devices typically have thermal coefficients of expansion exceeding that of the device to be packaged. A "loading" material (agent) having a coefficient of expansion significantly less than the "base" plastic material (molding compound), less than that of the die, and preferably zero or negative over a temperature range of interest, is mixed with the "base" plastic material to produce a plastic molding compound with a lower overall thermal coefficient of expansion. Titanium dioxide, zirconium oxide and silicon are discussed as loading agents. The loading material is mixed into the plastic molding compound in sufficient quantity to ensure that the resulting mixture exhibits an overall thermal coefficient of expansion that is more closely matched to that of the electronic device. Reduction of the absolute thermal coefficient of expansion of the plastic material (independent of any matching criteria) additionally serves to reduce thermal stress cracking of plastic package bodies during rapid thermal cycling, such as occurs during vapor soldering.

    摘要翻译： 用于封装（或支持）电子设备的塑料（或树脂）材料通常具有超过要包装的器件的热膨胀系数。 与目标温度范围相比，具有小于“基”塑料（模塑料）的膨胀系数的“负载”材料（试剂）与模具的相比，优选为零或负，与 “基”塑料材料生产具有较低总体热膨胀系数的塑料模塑料。 讨论了二氧化钛，氧化锆和硅作为负载剂。 将装载材料以足够的量混合到塑料模塑料中，以确保所得到的混合物表现出更接近于电子装置的热膨胀系数。 降低塑料材料的绝对热膨胀系数（与任何匹配标准无关）还可用于减少快速热循环期间塑料封装体的热应力开裂，例如在蒸气焊接过程中发生。

    Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints
    66.
    发明授权
    Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints 失效
    从较高层次创建和验证电子设计的低级描述的方法和系统，面向行为的描述，包括低级设计约束的估计和比较

    公开(公告)号：US5544066A

    公开(公告)日：1996-08-06

    申请号：US76729

    申请日：1993-06-14

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy ,  Doron Mintz

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  Vijay Nagasamy ,  Doron Mintz

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F11/26 ,  G06F17/50

    CPC分类号： G01R31/31704 ,  G01R31/318357 ,  G01R31/318364 ,  G01R31/318378 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5045

    摘要： A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized. Techniques are provided for constraint-driven partitioning of behavioral descriptions, and effective partitioning of high level descriptions for synthesis of multiple chips or blocks at the logic or register transfer levels. The partitioning technique is level-independent, and is integrated with the top-down design process, and takes into account constraints such as area, timing, power, package cost and testability. Iterative refinement is used to arrive at partitions that meet constraints imposed at high levels of abstraction.

    摘要翻译： 使用系统技术从高级描述和规范生成复杂数字设备的结构描述的方法，以映射和实施嵌入原始高级描述意图的语义的一致性。 设计活动本质上是在各种级别的设计表示上运行的一系列变革。 在每个级别，捕获意图（语义）和正式的软件操作，以得到更详细的级别，描述符合设计目标的硬件。 方法的重要特征是：捕获用户的概念，意图，规范，描述，约束和权衡; 建筑分区; 高级别的假设分析; 尺寸估算; 定时估计; 建筑权衡; 概念设计与实施估计; 和时间关闭。 该方法包括使用估计器，基于在多个实现的设计上收集的数据，用于在逻辑综合之前对设计进行分区和评估。 从结构描述中，容易实现设备的物理实现。 提供了用于行为描述的约束驱动分区的技术，以及用于在逻辑或寄存器传送级别合成多个芯片或块的高级描述的有效分区。 分区技术与层次无关，与自顶向下的设计流程相结合，并考虑到面积，时间，功耗，包装成本和可测试性等约束条件。 迭代细化用于达到满足在高抽象层次下施加的约束的分区。

    Afocal concentrator for low wavelength lithography, particularly for semiconductor lithography
    67.
    发明授权
    Afocal concentrator for low wavelength lithography, particularly for semiconductor lithography 失效
    用于低波长光刻的焦距聚焦器，特别适用于半导体光刻

    公开(公告)号：US5485243A

    公开(公告)日：1996-01-16

    申请号：US56553

    申请日：1993-04-30

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Joe Zelayeta

    IPC分类号： G03F7/20 ,  G03B27/00

    CPC分类号： G03F7/70008 ,  G03F7/702 ,  G03F7/70375 ,  Y10S430/167

    摘要： Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface. The concentrator is useful in for directing a stream of radiation from a continuously emitting source, such as from a pellet of Cobalt-60, onto the sensitized surface of the wafer when a shutter mechanism is incorporated either upstream (towards the source) or downstream (towards the wafer) from the concentrator.

    摘要翻译： 通过诸如X射线或γ射线的低波长辐射束在半导体晶片上的增感层中产生细微亚微米线特征和图案。 这种辐射流被集中器集中并准直，该集中器的输出设置在晶片敏感表面附近。 以这种方式，致敏表面可以从一个化学状态转变为另一个化学状态，基本上是逐点的。 通过移动光束或晶片中的一个或另一个，可以在致敏表面中转换线特征。 通常，去除敏化表面的未转化区域，以进一步处理敏化表面下面的层。 浓缩器可用于在将快门机构并入上游（朝向源）或下游（在源头）处引入来自连续发射源的辐射流，例如由钴-60颗粒沉积到晶片的致敏表面上（ 朝向晶片）。

    Testing and exercising individual, unsingulated dies on a wafer
    69.
    发明授权
    Testing and exercising individual, unsingulated dies on a wafer 失效
    在晶片上测试和运行单个，未加工的裸片

    公开(公告)号：US5442282A

    公开(公告)日：1995-08-15

    申请号：US908687

    申请日：1992-07-02

    申请人： Michael D. Rostoker ,  Carlos Dangelo ,  James Koford

    发明人： Michael D. Rostoker ,  Carlos Dangelo ,  James Koford

    IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  H01L21/82

    CPC分类号： G01R31/2856 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/006 ,  G01R31/2831

    摘要： Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

    摘要翻译： 来自外部系统的信号（包括探针）选择性地连接到具有最少数量的连接的半导体晶片上的多个未折叠的管芯和驻留在晶片上的电子选择机构。 电子选择机构通过晶片上的导线连接到各个管芯。 电子选择机构能够将外部信号（或连接外部探针）提供给单个管芯或模具组，并以电子方式“走过”整个多个未接合的管芯。 可以提供冗余的导线。 二极管和/或保险丝可以与导电线一起提供，以防止可能在导电线路中发生的各种故障。 还可以提供冗余电子选择机构以确保选择性地向未压制模具提供信号的能力。