公开(公告)号：US20060183313A1

公开(公告)日：2006-08-17

申请号：US11398723

申请日：2006-04-06

申请人： Su Tao

发明人： Su Tao

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/05124

摘要： A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

摘要翻译： 半导体封装包括半导体芯片，盖，多个迹线，柔性层，多个导电浆料和多个焊盘。 半导体芯片具有有源表面，背面和设置在有源表面上的多个接合焊盘。 盖子覆盖半导体芯片的有源表面。 迹线设置在盖和半导体芯片的有源表面之间，并且电连接到接合焊盘。 柔性层覆盖用于隔离迹线的半导体芯片的背面。 导电膏与导线电连接，焊盘与导电膏电连接。

公开(公告)号：US06939790B2

公开(公告)日：2005-09-06

申请号：US10693896

申请日：2003-10-28

申请人： Jau-Shoung Chen ,  Su Tao

发明人： Jau-Shoung Chen ,  Su Tao

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/441

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05172 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2924/0001 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184

摘要： A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned, so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls with a solidified material on the surface of each solder ball are disposed into each opening. Then, a reflow process is carried out, so that the solder balls bond with the metallic layer. Finally, the photoresist layer is removed.

摘要翻译： 提供了一种凸起工艺，其是在晶片上形成多个凸块的方法。 晶片具有钝化层和多个焊盘上的活性表面。 钝化层暴露有源表面上的焊盘。 在覆盖键合焊盘和钝化层的晶片的有源表面上形成粘附层。 在粘合层上形成金属层。 图案化粘合层和金属层，使得粘合层和金属层保持在焊盘的顶部。 在晶片的有源表面上形成光致抗蚀剂层。 光致抗蚀剂层具有暴露金属层的多个开口。 接下来，在每个开口中设置在每个焊球的表面上具有凝固材料的焊球。 然后，进行回流处理，使得焊球与金属层结合。 最后，去除光致抗蚀剂层。

公开(公告)号：US06927964B2

公开(公告)日：2005-08-09

申请号：US10604772

申请日：2003-08-15

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/525 ,  H02H5/00

CPC分类号： H01L24/12 ,  H01L23/3171 ,  H01L23/5258 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

摘要翻译： 具有能力的半导体器件可以防止燃烧的熔丝焊盘再次电连接，其中半导体器件包括凸块焊盘和晶片上的熔丝焊盘。 保险丝座包括具有用于电隔离的间隙的燃烧的保险丝座。 该半导体器件包括介于绝缘层上的绝缘层，该绝缘层基本上设置在烧结的熔丝焊盘的上方并填充间隙，以及设置在凸点焊盘上的凸块结构。 上述半导体器件还可以包括钝化层，其暴露凸块焊盘和烧焦的熔丝焊盘的一部分。 其中，电介质层在钝化层上方，覆盖烧结的熔丝垫的暴露部分并填充间隙。

公开(公告)号：US20050139979A1

公开(公告)日：2005-06-30

申请号：US11026763

申请日：2004-12-31

申请人： Su Tao ,  Yu-Fang Tsai

发明人： Su Tao ,  Yu-Fang Tsai

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/433 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

摘要翻译： 本发明涉及一种多芯片封装结构，包括第一基板，第一芯片，子封装和第一模塑料。 第一芯片附接到第一基板。 第一模塑料封装第一芯片，子封装和第一衬底的顶表面。 子封装的底表面附接到第一芯片。 该子组件包括第二衬底，第二芯片和第二模塑料。 第二基板具有顶表面和底表面，并且电连接到第一芯片。 第二芯片附接到第二芯片电连接到的第二基板的顶表面。 第二模塑料包封第二芯片和第二基板顶表面的一部分。 由此，可以减少由多个常规封装结构的平行布置引起的相对大的面积，并且不需要重新设计信号传输路径。

公开(公告)号：US06891274B2

公开(公告)日：2005-05-10

申请号：US10604794

申请日：2003-08-18

申请人： William Tze-You Chen ,  Ho-Ming Tong ,  Chun-Chi Lee ,  Su Tao ,  Jeng-Da Wu ,  Chih-Huang Chang ,  Po-Jen Cheng

发明人： William Tze-You Chen ,  Ho-Ming Tong ,  Chun-Chi Lee ,  Su Tao ,  Jeng-Da Wu ,  Chih-Huang Chang ,  Po-Jen Cheng

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/13109 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 μm to about 8 μm.

摘要翻译： 提供了凸块下的冶金层。 凸块下金属层形成在芯片的接触焊盘上，并且焊接块形成在球下冶金层之上。 凸块下冶金层包括粘合层，阻挡层和可润湿层。 粘合层直接形成在接触垫上。 在粘合层上形成由诸如镍 - 钒合金的材料制成的阻挡层。 由诸如铜的材料制成的可湿性层形成在阻挡层上。 可湿性层的总厚度范围为约3μm至约8μm。

公开(公告)号：US06846719B2

公开(公告)日：2005-01-25

申请号：US10248804

申请日：2003-02-20

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： H01L21/60 ,  H01L21/76

CPC分类号： H01L24/05 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.

摘要翻译： 在本发明中提供了晶片凸块制造工艺。 提供具有多个接合焊盘的晶片和暴露焊接焊盘的钝化层。 每个焊盘的表面具有凸块下的冶金层。 形成具有多个开口的图案化光致抗蚀剂层，这些开口暴露凸块下金属层。 之后进行固化工艺以固化图案化的光致抗蚀剂层。 进行焊膏填充处理以将焊膏填充到开口中。 进行回流处理以从开口中的焊膏形成凸起。 去除图案化的光致抗蚀剂层。

公开(公告)号：US06693364B2

公开(公告)日：2004-02-17

申请号：US10355152

申请日：2003-01-31

申请人： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

发明人： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

IPC分类号： H01L2348

CPC分类号： H01L31/0203 ,  H01L21/563 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/05599

摘要： An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.

摘要翻译： 一种光学集成电路元件封装，包括衬底，上部芯片，下部芯片，光学透明底部填充物和密封化合物。 衬底具有设置在衬底的表面上的多个焊球，与焊球电连接的多个接合焊盘，附接到衬底的另一个表面的盖以及露出罩的空腔。 上芯片设置有多个凸块，并且通过热间隙填充而粘附到空腔中的暴露盖。 下部芯片具有电连接到上部芯片的多个凸起的多个焊盘，并且具有电连接到该衬底的多个焊盘的多个凸块。 光学透明底部填充物设置在下部芯片和上部芯片之间。 密封组合物密封下部芯片和基板之间的空间。

公开(公告)号：US06617237B1

公开(公告)日：2003-09-09

申请号：US10248882

申请日：2003-02-27

申请人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

发明人： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

摘要： A lead-free solder bump fabrication process for producing a plurality of lead-free solder bumps over a wafer is provided. The lead-free solder bump fabrication process includes forming a lead-free pre-formed solder bump over each bonding pad on the wafer and then forming a patterned solder mask layer over the active surface of the wafer. The openings in the solder mask layer expose the respective lead-free pre-formed solder bumps on the wafer. Thereafter, lead-free solder material is deposited into the opening. The material composition of the lead-free solder material differs from the material composition of the lead-free pre-formed solder bump. A reflow process is conducted so that the lead-free pre-formed solder bump fuses with the lead-free solder material to form a lead-free solder bump. Finally, the solder mask layer is removed.

摘要翻译： 提供了一种用于在晶片上产生多个无铅焊料凸块的无铅焊料凸块制造工艺。 无铅焊料凸块制造工艺包括在晶片上的每个接合焊盘上形成无铅预成形焊料凸块，然后在晶片的有效表面上形成图案化的焊接掩模层。 焊接掩模层中的开口露出晶片上的相应的无铅预制焊料凸点。 此后，将无铅焊料材料沉积到开口中。 无铅焊料的材料组成不同于无铅预成形焊料凸块的材料组成。 进行回流处理，使得无铅预成形焊料凸块与无铅焊料材料熔合以形成无铅焊料凸块。 最后，去除焊接掩模层。

公开(公告)号：US06528393B2

公开(公告)日：2003-03-04

申请号：US09921890

申请日：2001-08-06

申请人： Su Tao

发明人： Su Tao

IPC分类号： H01L21301

CPC分类号： H01L29/0657 ,  H01L21/78 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54453 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method of dicing a wafer from the back side surface thereof comprises the steps of: providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips; forming a through structure corresponding to the scribe lines on the active surface of the wafer; and dicing the wafer from the back side surface of the wafer according to the through structure as positioning reference marks.

摘要翻译： 从其背面表面切割晶片的方法包括以下步骤：提供具有有源和背面的晶片，晶片的有源表面具有限定单个芯片的多个划线; 在所述晶片的有效表面上形成与所述划线对应的贯穿结构; 根据贯通结构将晶片从晶片的背面切割成定位基准标记。

公开(公告)号：US06342443B1

公开(公告)日：2002-01-29

申请号：US09346735

申请日：1999-07-02

申请人： Su Tao ,  Wei-Chung Wang ,  Jen-Kuang Fang

发明人： Su Tao ,  Wei-Chung Wang ,  Jen-Kuang Fang

IPC分类号： H01L2144

CPC分类号： H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/013 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

摘要： A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

摘要翻译： 首先提供具有C4焊料凸块的模具和聚合物基板的封装工艺。 然后将熔化的第二焊料喷射到形成第二焊料凸块的每个C4焊料凸块上。 在回流和调平焊料凸块之后，将模具翻转并与基板组合。 然后热处理随着管芯和衬底的组合进行，在聚合物衬底上形成具有塌陷控制的焊料凸块的倒装芯片封装。