中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

75 records (took 0.019 seconds)

    PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN
    63.
    发明申请
    PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN 审中-公开
    包装有嵌入元件的封装衬底

    公开(公告)号：US20140345930A1

    公开(公告)日：2014-11-27

    申请号：US14457338

    申请日：2014-08-12

    Applicant: Unimicron Technology Corporation

    Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

    IPC: H05K1/18 ,  H05K1/11

    CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

    Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

    Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

    METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN
    65.
    发明申请
    METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN 审中-公开
    嵌入式被动元件的包装衬底的制作方法

    公开(公告)号：US20140345125A1

    公开(公告)日：2014-11-27

    申请号：US14457343

    申请日：2014-08-12

    Applicant: Unimicron Technology Corporation

    Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

    IPC: H05K3/46 ,  H05K3/40

    CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

    Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

    Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

    ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
    66.
    发明申请
    ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME 有权
    电子设备及其制造方法

    公开(公告)号：US20140110713A1

    公开(公告)日：2014-04-24

    申请号：US14138968

    申请日：2013-12-23

    Applicant: Unimicron Technology Corporation

    Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu

    IPC: H01L31/02 ,  H01L31/20

    CPC classification number: H01L31/202 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645

    Abstract: An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated.

    Abstract translation: 提供一种电子设备及其制造方法。 该电子设备包括：光电二极管层; 形成在光电二极管层的第一表面上的布线层; 形成在所述布线层上的多个电接触焊盘; 形成在所述布线层和所述电接触焊盘上的钝化层; 形成在光电二极管层的第二表面上的抗反射层; 形成在所述抗反射层上的滤色层; 形成在抗反射层和滤色器层上的电介质层; 以及形成在电介质层上的微透镜层，允许滤色器层，电介质层和微透镜层限定其中定位电接触垫的有源区。 当电接触垫位于有源区域内时，可以消除用于非活性区域的衬底的区域。

    METHOD OF FABRICATING PACKAGING SUBSTRATE
    67.
    发明申请
    METHOD OF FABRICATING PACKAGING SUBSTRATE 审中-公开
    制作包装基材的方法

    公开(公告)号：US20140090794A1

    公开(公告)日：2014-04-03

    申请号：US14097656

    申请日：2013-12-05

    Applicant: Unimicron Technology Corporation

    Inventor： Tzyy-Jang Tseng ,  Chung-W. Ho

    IPC: H01L23/00

    CPC classification number: H01L24/19 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029

    Abstract: A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.

    Abstract translation: 封装基板包括第一介电层; 多个第一导电焊盘，其嵌入并暴露于所述第一介电层的第一表面; 第一电路层，其被嵌入并暴露于所述第一介电层的第二表面; 设置在第一电介质层中的多个第一金属凸块，每个第一金属凸块具有嵌入在第一电路层中的第一端和与第一端相对的第二端并且设置在第一导电焊盘之一上，导电种子层 设置在第一电路层和第一电介质层之间以及第一电路层和第一金属凸块之间; 布置在第一电路层和第一介电层上的叠层结构; 以及设置在所述积层结构上的多个第二导电焊盘。 包装衬底具有改善的超翘曲问题。

    FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS
    68.
    发明申请
    FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS 审中-公开
    包装嵌入式电容器的基板的制造方法

    公开(公告)号：US20140076492A1

    公开(公告)日：2014-03-20

    申请号：US14084901

    申请日：2013-11-20

    Applicant: UNIMICRON TECHNOLOGY CORPORATION

    Inventor： Chien-Kuang Lai ,  Chun-Chih Huang

    IPC: H01G4/30

    CPC classification number: H01G4/30 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H05K2201/10515 ,  H01L2924/00

    Abstract: A packaging substrate includes: a substrate having a core layer, a cavity penetrating the core layer and circuit layers formed on surfaces of the core layer; a first capacitor disposed in the cavity; a bonding layer formed on the first capacitor in the cavity of the substrate; a second capacitor disposed on the bonding layer so as to be received in the cavity; and a dielectric layer formed on the substrate and in the cavity for covering the first and second capacitors. By stacking the first and second capacitors in the cavity through the bonding layer, the single core layer is embedded with two layers of the capacitors to thereby meet the multi-function requirement.

    Abstract translation: 封装基板包括：具有芯层的基板，穿透芯层的空腔和形成在芯层表面上的电路层; 设置在所述空腔中的第一电容器; 形成在所述基板的空腔中的所述第一电容器上的接合层; 设置在所述接合层上以便容纳在所述空腔中的第二电容器; 以及形成在所述基板上和所述空腔中的用于覆盖所述第一和第二电容器的电介质层。 通过结合层将空腔中的第一和第二电容器堆叠起来，单芯层嵌有两层电容器，从而满足多功能要求。

    PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF
    69.
    发明申请
    PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF 审中-公开
    具有嵌入式半导体元件的封装结构及其制造方法

    公开(公告)号：US20140035138A1

    公开(公告)日：2014-02-06

    申请号：US14046000

    申请日：2013-10-04

    Applicant: Unimicron Technology Corporation

    Inventor： Shih-Ping Hsu ,  I-Ta Tsai

    IPC: H01L23/498

    CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

    Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

    Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于包围物的抗弯曲性，防止了积层结构的翘曲。

Patent Agency Ranking