公开(公告)号：US10056487B2

公开(公告)日：2018-08-21

申请号：US15365538

申请日：2016-11-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

公开(公告)号：US10056293B2

公开(公告)日：2018-08-21

申请号：US14335328

申请日：2014-07-18

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/84 ,  H01L21/74 ,  H01L27/12 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/1203

Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.

公开(公告)号：US09997472B2

公开(公告)日：2018-06-12

申请号：US15401539

申请日：2017-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/66 ,  H01L23/00 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  B82Y10/00

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US09954062B2

公开(公告)日：2018-04-24

申请号：US15134174

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/40 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US09917057B2

公开(公告)日：2018-03-13

申请号：US15361757

申请日：2016-11-28

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Szu-Lin Cheng ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L21/324 ,  H01L23/528 ,  H01L21/3105

CPC classification number: H01L23/53228 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer.

公开(公告)号：US09859430B2

公开(公告)日：2018-01-02

申请号：US14755029

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/308 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed.

公开(公告)号：US20170256655A1

公开(公告)日：2017-09-07

申请号：US15603945

申请日：2017-05-24

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

公开(公告)号：US09748348B2

公开(公告)日：2017-08-29

申请号：US15400178

申请日：2017-01-06

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Robert H. Dennard ,  Isaac Lauer ,  Ramachandran Muralidhar

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/42356 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming a MOSFET device is provided including: providing an SOI wafer; forming a dummy gate oxide and dummy gates on portions of the SOI layer that serve as channel regions of the device; forming spacers and doped source/drain regions in the SOI layer on opposite sides of the dummy gates; depositing a gap fill dielectric; removing the dummy gates/gate oxide; recessing areas of the SOI layer exposed by removal of the dummy gates forming one or more u-shaped grooves that extend part-way through the SOI layer such that a thickness of the SOI layer remaining in the channel regions is less than a thickness of the SOI layer in the doped source/drain regions under the spacers; and forming u-shaped replacement gate stacks in the u-shaped grooves such that u-shaped channels are formed in fully depleted regions of the SOI layer adjacent to the u-shaped replacement gate stacks.

公开(公告)号：US20170194325A1

公开(公告)日：2017-07-06

申请号：US15464213

申请日：2017-03-20

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Robert H. Dennard ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Ghavam G. Shahidi

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/308 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/3081 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

公开(公告)号：US20170170270A1

公开(公告)日：2017-06-15

申请号：US15245851

申请日：2016-08-24

Applicant: International Business Machines Corporation

Inventor： Jack O. Chu ,  Szu Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/762 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.