公开(公告)号：US06399733B1

公开(公告)日：2002-06-04

申请号：US09686063

申请日：2000-10-11

申请人： Shigeyuki Yamamoto ,  Naoki Yasuda ,  Motohisa Taguchi

发明人： Shigeyuki Yamamoto ,  Naoki Yasuda ,  Motohisa Taguchi

IPC分类号： C08G7706

CPC分类号： C08G77/04 ,  C08G77/06 ,  C08G77/34

摘要： A process for preparing a highly pure silicone ladder polymer of the general formula (1): wherein R1 and R2 represent F, H, a lower alkyl group, an alkenyl group, an aryl group, a lower fluorinated alkyl group, a fluorinated alkenyl group or a fluorinated aryl group; R3, R4, R5 and R6 each represents H, a lower alkyl group or a lower fluorinated alkyl group; and n represents an integer of 5 to 10000, which comprises: (a) a step of obtaining a prepolymer in which at least one organosilane compound is dissolved in an organic solvent and hydrolyzed with ultrapure water; (b) a step of washing the obtained prepolymer with ultrapure water; and, (c) a step of dissolving the washed prepolymer in an organic solvent and heating without a catalyst.

摘要翻译： 制备通式（1）的高纯硅树脂聚合物的方法：其中R1和R2表示F，H，低级烷基，烯基，芳基，低级氟化烷基，氟化烯基 或氟化芳基; R3，R4，R5和R6各自表示H，低级烷基或低级氟化烷基; n表示5〜10000的整数，其包括：（a）获得其中至少一种有机硅烷化合物溶解在有机溶剂中并用超纯水水解的预聚物的步骤;（b） 超纯水预聚物; 和（c）将洗过的预聚物溶解在有机溶剂中并加热而不用催化剂的步骤。

公开(公告)号：US06180320B2

公开(公告)日：2001-01-30

申请号：US09371499

申请日：1999-08-10

申请人： Takayuki Saito ,  Takeo Ishibashi ,  Toshiyuki Toyoshima ,  Kanji Sugino ,  Naoki Yasuda ,  Tadashi Miyagi

发明人： Takayuki Saito ,  Takeo Ishibashi ,  Toshiyuki Toyoshima ,  Kanji Sugino ,  Naoki Yasuda ,  Tadashi Miyagi

IPC分类号： G03F7039

CPC分类号： G03F7/40 ,  H01L21/0274 ,  H01L21/0338

摘要： There is described a method of stably manufacturing a fine resist pattern narrower than the wavelength of exposing light from a stepper. Under the method, a resist pattern is formed on a semiconductor substrate through use of an acid catalyst chemically-amplified photoresist, and an organic film which includes an acid or which produces an acid on exposure to light is formed on the surface of the semiconductor substrate including the resist pattern. The organic film is then subjected to a heat treatment to thereby diffuse an acid. The surface layer of the resist pattern is made soluble in an alkaline developer, and the surface layer of the resist pattern is removed through use of the alkaline developer. As a result, a fine resist pattern is formed.

摘要翻译： 描述了一种稳定地制造比曝光来自步进器的光的波长窄的精细抗蚀剂图案的方法。 在该方法下，通过使用酸催化剂化学扩增的光致抗蚀剂在半导体衬底上形成抗蚀剂图案，并且在半导体衬底的表面上形成包含酸或在曝光时产生酸的有机膜 包括抗蚀剂图案。 然后对有机膜进行热处理，从而扩散酸。 抗蚀剂图案的表面层可溶于碱性显影剂，通过使用碱性显影剂除去抗蚀剂图案的表面层。 结果，形成精细的抗蚀剂图案。

公开(公告)号：US5586006A

公开(公告)日：1996-12-17

申请号：US573577

申请日：1995-12-15

申请人： Kiyotaka Seyama ,  Shunichi Kikuchi ,  Makoto Sumiyoshi ,  Naoki Yasuda ,  Minoru Hirano ,  Hitoshi Nori

发明人： Kiyotaka Seyama ,  Shunichi Kikuchi ,  Makoto Sumiyoshi ,  Naoki Yasuda ,  Minoru Hirano ,  Hitoshi Nori

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L25/04 ,  H01L25/065 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46 ,  H05K7/20

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H05K1/141 ,  H01L2224/16 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H05K2201/0317 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/467 ,  Y02P70/611

摘要： A multi-chip module includes a base board, a thin-film multi-layer circuit board which is provided on a first surface of the base board and has a multi-layer structure in which insulating layers and wiring conductors are stacked, circuit elements mounted on a main surface of the thin-film multi-layer circuit board, and terminals which are attached to the main surface of the thin-film multi-layer circuit board and electrically connect the wiring conductors to circuits formed on a wiring board on which the multi-chip module is mounted.

摘要翻译： 多芯片模块包括基板，薄膜多层电路板，其设置在基板的第一表面上，并且具有层叠绝缘层和布线导体的多层结构，安装有电路元件 在薄膜多层电路板的主表面上，以及端子，其安装在薄膜多层电路板的主表面上，并将布线导体电连接到形成在其上的电路板上的电路 安装了多芯片模块。

公开(公告)号：US08846148B2

公开(公告)日：2014-09-30

申请号：US12084568

申请日：2006-11-15

申请人： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Tetsuya Yamamoto ,  Yasutaka Nakatani ,  Takuya Kamiyama

发明人： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Tetsuya Yamamoto ,  Yasutaka Nakatani ,  Takuya Kamiyama

IPC分类号： C23C16/00 ,  C07F5/02 ,  C23C16/30 ,  H01L21/314 ,  C23C16/34 ,  H01L21/318

CPC分类号： C23C16/342 ,  C07F5/02 ,  C23C16/30 ,  H01L21/314 ,  H01L21/318

摘要： A composition for chemical vapor deposition film-formation comprising a borazine compound represented by the Chemical Formula 1 satisfying at least one of a condition that content of each halogen atom in the composition is 100 ppb or less or a condition that content of each metal element in the composition is 100 ppb or less. In the Chemical Formula 1, R1 may be the same or different, and is hydrogen atom, alkyl group, alkenyl group or alkynyl group, and at least one thereof is hydrogen atom; R2 may be the same or different, and is hydrogen atom, alkyl group, alkenyl group or alkynyl group, and at least one thereof is alkyl group, alkenyl group or alkynyl group.

摘要翻译： 一种用于化学气相沉积膜形成的组合物，其包含由化学式1表示的环硼氮烷化合物，其满足组合物中每个卤素原子的含量为100ppb以下的条件中的至少一种或每种金属元素的含量 组合物为100ppb以下。 在化学式1中，R 1可以相同或不同，为氢原子，烷基，链烯基或炔基，其中至少一个为氢原子; R2可以相同或不同，为氢原子，烷基，烯基或炔基，其中至少一个为烷基，烯基或炔基。

公开(公告)号：US08723248B2

公开(公告)日：2014-05-13

申请号：US13404073

申请日：2012-02-24

申请人： Naoki Yasuda ,  Jun Fujiki

发明人： Naoki Yasuda ,  Jun Fujiki

IPC分类号： H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/792

摘要： In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.

摘要翻译： 在一个实施例中，提供了一种非易失性半导体存储装置。 该装置包括：多个非易失性存储单元。 每个非易失性存储单元包括：第一半导体层，包括第一源极区，第一漏极区和第一沟道区; 形成在所述第一沟道区上的块绝缘膜; 形成在所述块绝缘膜上的电荷存储层; 形成在电荷存储层上的隧道绝缘膜; 形成在所述隧道绝缘膜上并且包括第二源极区域，第二漏极区域和第二沟道区域的第二半导体层。 第二沟道区形成在隧道绝缘膜上，使得隧道绝缘膜位于第二源区和第二漏区之间。 第一沟道区的掺杂剂杂质浓度高于第二沟道区的掺杂剂杂质浓度。

公开(公告)号：US08674430B2

公开(公告)日：2014-03-18

申请号：US13428111

申请日：2012-03-23

申请人： Naoki Yasuda ,  Masaru Kito

发明人： Naoki Yasuda ,  Masaru Kito

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

摘要翻译： 根据一个实施例，控制栅极形成在半导体衬底上并且包括圆柱形通孔。 在通孔内的控制栅极的侧表面上形成块绝缘膜，电荷存储膜，隧道绝缘膜和半导体层。 隧道绝缘膜包括具有SiO 2作为基材的第一绝缘膜，并且包含通过添加来降低基材的带隙的元素。 元素的密度和密度梯度从半导体层向电荷存储膜单调增加。

公开(公告)号：US08674046B2

公开(公告)日：2014-03-18

申请号：US12558810

申请日：2009-09-14

申请人： Hideharu Nobutoki ,  Teruhiko Kumada ,  Toshiyuki Toyoshima ,  Naoki Yasuda ,  Suguru Nagae

发明人： Hideharu Nobutoki ,  Teruhiko Kumada ,  Toshiyuki Toyoshima ,  Naoki Yasuda ,  Suguru Nagae

IPC分类号： C08G79/08 ,  C08G73/06 ,  C08G79/00 ,  C08G73/00

CPC分类号： H01L21/02118 ,  H01L21/02164 ,  H01L21/312 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L29/51 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00

摘要： A low dielectric constant material having an excellent water resistance obtained by heat-treating a borazine compound of the formula (1-2): or an inorganic or organic compound having a group derived from the borazine compound (1-2) to undergo a condensation reaction, thereby producing an oligomer or polymer, wherein R1 to R6 are independently a hydrogen atom, an alkyl group having 1 to 20 carbon atoms, an aryl group, a substituted aryl group, an alkenyl group, an amino group, an alkylamino group, an alkoxyl group, a thioalkoxyl group, a carbonyl group, a silyl group, an alkylsilyl group, a phosphino group, an alkylphosphino group, or a group of the formula: Si(OR7)(OR8)(OR9), and at least one of R1 to R6 is not hydrogen atom.

摘要翻译： 通过热处理式（1-2）的环硼氮烷化合物获得的具有优异耐水性的低介电常数材料或具有衍生自环硼氮烷化合物（1-2）的基团的无机或有机化合物进行缩合 反应，由此制备低聚物或聚合物，其中R 1至R 6独立地为氢原子，具有1至20个碳原子的烷基，芳基，取代的芳基，烯基，氨基，烷基氨基， 烷氧基，硫代烷氧基，羰基，甲硅烷基，烷基甲硅烷基，膦基，烷基膦基或下式的基团：Si（OR7）（OR8）（OR9），和至少一个 的R 1至R 6不是氢原子。

公开(公告)号：US20130160711A1

公开(公告)日：2013-06-27

申请号：US13772795

申请日：2013-02-21

申请人： Teruhiko KUMADA ,  Hideharu Nobutoki ,  Naoki Yasuda

发明人： Teruhiko KUMADA ,  Hideharu Nobutoki ,  Naoki Yasuda

IPC分类号： B05D1/00

CPC分类号： H01L21/02274 ,  C23C16/30 ,  C23C16/342 ,  C23C16/511 ,  H01J37/32532 ,  H01L21/02112 ,  H01L21/02205 ,  H01L21/318

摘要： A plasma CVD apparatus including a reaction chamber including an inlet for supplying a compound including a borazine skeleton, a feeding electrode, arranged within the reaction chamber, for supporting a substrate and being applied with a negative charge, and a plasma generating mechanism, arranged opposite to the feeding electrode via the substrate, for generating a plasma within the reaction chamber. A method forms a thin film wherein a thin film is formed by using a compound including a borazine skeleton as a raw material, and a semiconductor device includes a thin film formed by such a method as an insulating film. The apparatus and method enable to produce a thin film wherein low dielectric constant and high mechanical strength are stably maintained for a long time and insulating characteristics are secured.

摘要翻译： 一种等离子体CVD装置，包括反应室，该反应室包括用于供给包含环硼氮烷骨架的化合物的入口，设置在反应室内的供电电极，用于支撑基板并施加负电荷;以及等离子体产生机构， 经由衬底到达馈电电极，用于在反应室内产生等离子体。 一种方法形成薄膜，其中通过使用包含环硼氮烷骨架的化合物作为原料形成薄膜，并且半导体器件包括通过诸如绝缘膜的方法形成的薄膜。 该装置和方法能够制造其中低介电常数和高机械强度长时间稳定地保持并且确保绝缘特性的薄膜。

公开(公告)号：US08467241B2

公开(公告)日：2013-06-18

申请号：US13246996

申请日：2011-09-28

申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

IPC分类号： G11C11/34

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

公开(公告)号：US20120326224A1

公开(公告)日：2012-12-27

申请号：US13418620

申请日：2012-03-13

申请人： Shigeru KAWANAKA ,  Kosuke Tatsumura ,  Naoki Yasuda ,  Jun Fujiki ,  Atsushi Kawasumi

发明人： Shigeru KAWANAKA ,  Kosuke Tatsumura ,  Naoki Yasuda ,  Jun Fujiki ,  Atsushi Kawasumi

IPC分类号： H01L27/088

CPC分类号： H01L21/28282 ,  G11C11/22 ,  G11C11/412 ,  G11C14/0081 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/11568 ,  H01L27/11807 ,  H01L29/518 ,  H01L29/792

摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.

摘要翻译： 半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。 半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子 栅电极与通道相比。