公开(公告)号：US20150162245A1

公开(公告)日：2015-06-11

申请号：US14596185

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Bing-Siang CHEN ,  Chien-Hui CHEN ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L21/78 ,  H01L25/00

CPC classification number: H01L21/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在所述第一芯片上的第二芯片，其中所述第二芯片的侧表面是化学蚀刻表面; 以及设置在所述第一芯片和所述第二芯片之间的结合体，使得所述第一芯片和所述第二芯片彼此结合。

公开(公告)号：US20150123231A1

公开(公告)日：2015-05-07

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US20150061102A1

公开(公告)日：2015-03-05

申请号：US14470159

申请日：2014-08-27

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14683 ,  H01L27/1469 ,  H01L31/02005 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/1204 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Abstract translation: 提供了一种电子器件封装及其制造方法。 首先，提供半导体衬底，并且从凹部蚀刻其上表面。 第一隔离层形成在凹槽的上表面和侧壁上。 形成导电部件以实现凹部，并且在第一隔离层上形成导电焊盘以连接导电部件。 电子设备与晚餐表面上的半导体衬底组合，其中电子设备具有电连接到导电焊盘的连接焊盘。 半导体衬底从其下表面变薄以暴露导电部件。 第二隔离层形成在下表面下方并具有用于暴露导电部分的开口。 在第二隔离层下方和开口中形成再分布金属线，以电连接到导电部分。

公开(公告)号：US20140332968A1

公开(公告)日：2014-11-13

申请号：US14339323

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN

IPC: H01L23/498

CPC classification number: H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20140225276A1

公开(公告)日：2014-08-14

申请号：US14171734

申请日：2014-02-03

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48151 ,  H01L2224/73207 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract translation: 本公开的一个实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 电线层，其设置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中; 位于所述导线层和所述半导体基板之间的绝缘层; 设置在所述第一表面上的芯片; 以及设置在所述芯片和所述第一表面之间的导电结构。

公开(公告)号：US20240304582A1

公开(公告)日：2024-09-12

申请号：US18431627

申请日：2024-02-02

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L24/16 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H05K1/181 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13155 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/16225 ,  H01L2924/1431

Abstract: A circuit substrate in a chip package is provided. The circuit substrate includes first and second insulating layers covering opposite first and second surfaces of the semiconductor substrate, respectively. The circuit substrate also includes first and second pads disposed in the first and second insulating layers, respectively, and laterally separated from an opening that extends from the first surface to the second surface of the semiconductor substrate. The circuit substrate further includes first and second under bump metallization (UBM) layers disposed on the first and second pads, respectively. The first UBM layer has a surface protruding above the first insulating layer, and the second UBM layer extends from the second pad onto the second insulating layer, and is partially recessed into the second insulating layer to form a concave surface.

公开(公告)号：US20230230933A1

公开(公告)日：2023-07-20

申请号：US18149029

申请日：2022-12-30

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Chaung-Lin LAI ,  Shu-Ming CHANG ,  Tsang-Yu LIU

IPC: H01L23/544 ,  H01L27/146

CPC classification number: H01L23/544 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2223/54433

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

公开(公告)号：US20210104455A1

公开(公告)日：2021-04-08

申请号：US17037151

申请日：2020-09-29

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.

公开(公告)号：US20170077158A1

公开(公告)日：2017-03-16

申请号：US15258594

申请日：2016-09-07

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yi-Ming CHANG ,  Hsin KUAN

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14685 ,  H01L2224/11

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

Abstract translation: 提供了包括基板的芯片封装。 基板具有与其相对的第一表面和第二表面。 衬底包括感测区域。 盖板在第一表面上并覆盖感测区域。 屏蔽层覆盖盖板的侧壁并朝向第二表面延伸。 屏蔽层具有与盖板相邻的内表面，并具有远离盖板的外表面。 朝向第二表面延伸的外表面的长度小于朝向第二表面延伸的内表面的长度，并且不小于盖板的侧壁的长度。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20170053848A1

公开(公告)日：2017-02-23

申请号：US15237287

申请日：2016-08-15

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Po-Chang HUANG ,  Tsang-Yu LIU ,  Yu-Lung HUANG ,  Chi-Chang LIAO

IPC: H01L23/31 ,  H01L23/08 ,  G06K9/00 ,  H01L21/56

CPC classification number: H01L23/3121 ,  G06K9/00013 ,  G06K9/0002 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L2224/11

Abstract: A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.

Abstract translation: 提供感测模块。 感测模块​​包括感测装置。 感测装置包括具有第一表面和与其相对的第二表面的第一基底。 感测装置还包括与第一表面相邻的感测区域和第一表面上的导电垫片。 感测装置还包括在第二表面上的再分配层，并且电连接到导电垫。 感测模块​​还包括结合到感测装置的第二基板和盖板，使得感测装置在第二基板和盖板之间。 导电焊盘通过再分布层与第二基板电连接。 感测模块​​还包括填充在第二基板和盖板之间以封装感测装置的封装层。