公开(公告)号：US5840597A

公开(公告)日：1998-11-24

申请号：US789515

申请日：1997-01-27

Applicant: Siegbert Hartauer

Inventor： Siegbert Hartauer

IPC: B81B3/00 ,  G01L1/18 ,  G01P15/08 ,  G01P15/12 ,  G01P15/125 ,  H01L21/00

CPC classification number: B81C1/00246 ,  G01L1/18 ,  G01P15/0802 ,  G01P15/123 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/0109 ,  B81B2203/0315 ,  B81C2201/0136 ,  B81C2201/014 ,  B81C2203/0728 ,  B81C2203/0735

Abstract: A semiconductor device with a force and/or acceleration sensor (12), which has a spring-mass system (14, 16) responsive to the respective quantity to be measured and whose mass (16) bears via at least one resilient support element (14) on a semiconductor substrate (20). The semiconductor substrate (20) and the spring-mass system (14, 16) are integral components of a monocrystalline semiconductor crystal (10) with a IC-compatible structure. The three-dimensional structural form of the spring-mass system (12) is produced by anisotropic semiconductor etching, defined P/N junctions of the semiconductor layer arrangement functioning as etch stop means in order to more particularly create a gap (22) permitting respective movement of the mass (16) between the mass (16) and the semiconductor substrate (20).

Abstract translation: 一种具有力和/或加速度传感器（12）的半导体器件，其具有响应于待测量的相应量的弹簧质量系统（14,16），并且其质量（16）经由至少一个弹性支撑元件（ 14）在半导体衬底（20）上。 半导体衬底（20）和弹簧质量系统（14,16）是具有IC兼容结构的单晶半导体晶体（10）的组成部分。 通过各向异性半导体蚀刻制造弹簧质量体系（12）的三维结构形式，作为蚀刻停止装置的半导体层布置的限定的P / N结，以更具体地形成允许相应的间隙（22） 质量块（16）和半导体衬底（20）之间的质量块（16）的移动。

公开(公告)号：US5332469A

公开(公告)日：1994-07-26

申请号：US14025

申请日：1993-02-05

Applicant: Carlos H. Mastrangelo

Inventor： Carlos H. Mastrangelo

IPC: G01L9/12 ,  B23P15/00 ,  B81B3/00 ,  B81C1/00 ,  G01L9/00 ,  G01L13/06 ,  G01P15/08 ,  H01L21/306 ,  H01L21/68 ,  H01L29/84 ,  B44C1/22 ,  C03C15/00 ,  C23F1/00

CPC classification number: B81C1/00476 ,  B23P15/00 ,  B81B3/0013 ,  B81C1/0092 ,  B81C1/00944 ,  G01L9/0042 ,  G01L9/0073 ,  G01P15/0802 ,  H01L21/6835 ,  B81B2201/0264 ,  B81C2201/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10S438/977 ,  Y10T29/49103

Abstract: A surface layer and a sacrificial layer are deposited on a substrate. A conductive structural layer bridges over the sacrificial layer and is anchored to the surface layer for creating paired conductive areas. A backside opening is etched in the substrate for defining a flexible diaphragm layer of reduced thickness. The sacrificial layer is removed so that pressures exerted on the backside opening will cause a change in capacitance between the paired conductive areas. Temporary posts support the conductive structural layer as the sacrificial layer is removed.

Abstract translation: 表面层和牺牲层沉积在基底上。 导电结构层桥接在牺牲层上并且锚固到表面层以产生成对的导电区域。 背衬开口被蚀刻在衬底中以限定厚度减小的柔性隔膜层。 牺牲层被去除，使得施加在背侧开口上的压力将导致成对的导电区域之间的电容变化。 当牺牲层被去除时，临时柱支撑导电结构层。

公开(公告)号：US20240304453A1

公开(公告)日：2024-09-12

申请号：US18665377

申请日：2024-05-15

Applicant: ULVAC, INC.

Inventor： TAICHI SUZUKI ,  Yasuhiro MORIKAWA ,  Kenta DOI ,  Toshiyuki NAKAMURA

IPC: H01L21/3065 ,  B81C1/00 ,  C23C14/02 ,  C23C14/34 ,  H01J37/32 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/30655 ,  B81C1/00531 ,  B81C1/00619 ,  C23C14/021 ,  C23C14/34 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/014 ,  H01J2237/3321 ,  H01J2237/3341 ,  H01J2237/3342

Abstract: The present disclosure provides an etching method that includes a resist pattern-forming step of forming a resist layer on a target object, the resist layer being formed of a resin, the resist layer having a resist pattern; an etching step of etching the target object via the resist layer having the resist pattern; and a resist protective film-forming step of forming a resist protective film on the resist layer. The etching step is repetitively carried out multiple times. A processing gas, used in the resist protective film-forming step, includes a gas capable of forming SixOyαz; wherein a is any one of F, Cl, H, and CkHl; and each of x, y, z, k, is a selected non-zero value. After the etching steps are repetitively carried out multiple times, the resist protective film-forming step is performed.

公开(公告)号：US20230382715A1

公开(公告)日：2023-11-30

申请号：US18324533

申请日：2023-05-26

Applicant: COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Samer DAGHER ,  Loïc JOET

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81C1/00158 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0361 ,  B81B2203/04 ,  B81B2207/11 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/0104

Abstract: An electroacoustic transducer includes a frame; an element movable relative to the frame, the movable element including a membrane; an internal cavity called back volume, subjected to a reference pressure and delimited by the movable element and walls belonging to the frame; in which transducer at least one of the walls delimiting the back volume includes at least one sealed cavity and in which a pressure lower than the reference pressure prevails in the at least one sealed cavity.

公开(公告)号：US11818563B2

公开(公告)日：2023-11-14

申请号：US17830448

申请日：2022-06-02

Applicant: Fortemedia, Inc.

Inventor： Li-Jen Chen ,  Yu-Xuan Xu ,  Yu-Ting Cheng ,  Shih-Chin Gong

IPC: H04R9/06 ,  B81C1/00 ,  H04R7/04 ,  H04R7/16 ,  H04R1/02 ,  H04R31/00 ,  H04R9/04 ,  H04R9/02

CPC classification number: H04R9/06 ,  B81C1/00587 ,  H04R1/025 ,  H04R7/04 ,  H04R7/16 ,  H04R9/025 ,  H04R9/047 ,  H04R31/003 ,  H04R31/006 ,  B81C2201/014 ,  B81C2201/0132 ,  B81C2201/0133 ,  H04R2307/025

Abstract: A package structure of a micro speaker is provided. The package structure includes a substrate, a diaphragm, a coil, an etch stop layer, a carrier board, a permanent magnetic element, and package lid. The substrate has a hollow chamber. The diaphragm is suspended over the hollow chamber. The coil is embedded in the diaphragm. The etch stop layer is positioned below the coil and overlaps the coil in the direction that is perpendicular to the top surface of the diaphragm. The etch stop layer is made of a metal material. The carrier board is disposed on the bottom surface of the substrate. The permanent magnetic element is disposed on the carrier board and in the hollow chamber. The package lid is wrapped around the substrate and the diaphragm, and has a lid opening that exposes a portion of the top surface of the diaphragm.

公开(公告)号：US20230357000A1

公开(公告)日：2023-11-09

申请号：US17811109

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Jung Chen

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/0176

Abstract: A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.

公开(公告)号：US20230271825A1

公开(公告)日：2023-08-31

申请号：US17923648

申请日：2020-06-28

Applicant: RESEARCH INSTITUTE OF TSINGHUA UNIVERSITY IN SHENZHEN ,  TSINGHUA UNIVERSITY

Inventor： Quanshui ZHENG ,  Xiaojian XIANG

IPC: B81C1/00 ,  B81B7/02

CPC classification number: B81C1/00357 ,  B81B7/02 ,  B81B2201/038 ,  B81B2203/04 ,  B81C2201/0102 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2203/032 ,  B81C2203/0136 ,  B81C2201/0181

Abstract: Provided is an atomic-smooth device with a microstructure. The device includes, from the bottom to top, a substrate, a bonding material, a second dielectric layer on the substrate, the microstructure, and a first dielectric layer, where a surface of the first dielectric layer is an atomic-smooth surface. Further provided is a method for preparing an atomic-smooth device with a microstructure to effectively avoid pits or burrs generated when the existing microstructure is machined.

公开(公告)号：US11667523B2

公开(公告)日：2023-06-06

申请号：US17121955

申请日：2020-12-15

Applicant: Texas Instruments Incorporated

Inventor： Simon Joshua Jacobs

IPC: B81C1/00 ,  B81B3/00 ,  G02B26/08 ,  H01L33/48 ,  B81B7/00 ,  G02B1/115

CPC classification number: B81C1/00317 ,  B81B3/0083 ,  B81B7/0067 ,  B81C1/00595 ,  G02B1/115 ,  G02B26/0833 ,  H01L33/483 ,  H01L33/486 ,  B81B2201/042 ,  B81B2207/015 ,  B81C1/00047 ,  B81C1/00119 ,  B81C1/00261 ,  B81C1/00269 ,  B81C2201/014 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0145 ,  B81C2203/0735 ,  B81C2203/0771

Abstract: An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.

公开(公告)号：US20190090067A1

公开(公告)日：2019-03-21

申请号：US16128288

申请日：2018-09-11

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Matteo PERLETTI ,  Federico VERCESI ,  Silvia ADORNO ,  Giorgio ALLEGATO

IPC: H04R19/04 ,  B81B7/00 ,  B81C1/00 ,  H04R19/00 ,  H04R1/28

CPC classification number: H04R19/04 ,  B81B7/0029 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/012 ,  B81C1/00309 ,  B81C1/00626 ,  B81C2201/014 ,  B81C2201/0198 ,  H04R1/086 ,  H04R1/2807 ,  H04R19/005 ,  H04R31/00 ,  H04R2201/003

Abstract: A method for manufacturing a filtering module comprising the steps of: forming a multilayer body comprising a filter layer of semiconductor material and having a thickness of less than 10 μm, a first structural layer coupled to a first side of the filter layer, and a second structural layer coupled to a second side, opposite to the first side, of the filter layer; forming a recess in the first structural layer, which extends throughout its thickness; removing selective portions, exposed through the recess, of the filter layer to form a plurality of openings, which extend throughout the thickness of the filter layer; and completely removing the second structural layer to connect fluidically the first and second sides of the filter layer, thus forming a filtering membrane designed to inhibit passage of contaminating particles.

公开(公告)号：US20190016591A1

公开(公告)日：2019-01-17

申请号：US16137914

申请日：2018-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Huang Chiu ,  Weng-Yi Chen ,  Kuan-Yu Wang

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/0006 ,  B81B2201/0214 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0384 ,  B81B2203/0392 ,  B81B2203/04 ,  B81C1/00428 ,  B81C2201/014 ,  B81C2203/0735 ,  B81C2203/0771

Abstract: A manufacturing method for a semiconductor structure is disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.