公开(公告)号：US20100142878A1

公开(公告)日：2010-06-10

申请号：US12504607

申请日：2009-07-16

Applicant: Jeong Woo PARK ,  Jongbum You ,  Gyungock Kim

Inventor： Jeong Woo PARK ,  Jongbum You ,  Gyungock Kim

IPC: G02F1/01 ,  G02B6/12 ,  H01L21/22

CPC classification number: G02F1/025 ,  G02F2001/0156 ,  G02F2201/063 ,  G02F2201/12 ,  G02F2202/105 ,  G02F2202/32

Abstract: An absorption modulator is provided. The absorption modulator includes a substrate, an insulation layer disposed on the substrate, and a waveguide having a P-I-N diode structure on the insulation layer. Absorptance of an intrinsic region in the P-I-N diode structure is varied when modulating light inputted to the waveguide. The absorption modulator obtains the improved characteristics, such as high speed, low power consumption, and small size, because it greatly reduces the cross-sectional area of the P-I-N diode structure.

Abstract translation: 提供吸收调制器。 吸收调制器包括基板，设置在基板上的绝缘层，以及在绝缘层上具有P-I-N二极管结构的波导。 当调制输入到波导的光时，P-I-N二极管结构中的本征区域的吸收变化。 吸收调制器由于大大降低了P-I-N二极管结构的截面面积而获得了高速，低功耗，小尺寸等改进的特性。

公开(公告)号：US20100018633A1

公开(公告)日：2010-01-28

申请号：US12408366

申请日：2009-03-20

Applicant: Myung-Sam KANG ,  Jung-Hyun PARK ,  Jeong-Woo PARK ,  Ji-Eun KIM

Inventor： Myung-Sam KANG ,  Jung-Hyun PARK ,  Jeong-Woo PARK ,  Ji-Eun KIM

IPC: B32B37/00

CPC classification number: B32B38/04 ,  B32B38/10 ,  B32B2038/0092 ,  B32B2038/047 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1064 ,  Y10T156/1082

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于将一层连接到另一层的通路的印刷电路板的制造方法可以包括在载体的一个表面上形成电路图案; 在载体的一个表面上处理与通孔对应的孔; 将载体的表面压缩到绝缘体的一个表面中; 移除载体; 处理绝缘体上的通孔，对应于孔的位置; 并且在通孔中形成导电材料，从而容易地加工用于形成通孔的孔，并且具有高的设计自由度

公开(公告)号：US20100002978A1

公开(公告)日：2010-01-07

申请号：US12517802

申请日：2007-08-07

Applicant: Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

Inventor： Jeong-Woo Park ,  Gyungock Kim ,  Young-Ahn Leem ,  Hyun-Soo Kim ,  Bongki Mheen

IPC: G02F1/035 ,  G02B6/12

CPC classification number: H01L31/12 ,  H01L27/144

Abstract: Provided are a photoelectric device using a PN diode and a silicon integrated circuit (IC) including the photoelectric device. The photoelectric device includes: a substrate; and an optical waveguide formed as a PN diode on the substrate, wherein a junction interface of the PN diode is formed in a direction in which light advances; and an electrode applying a reverse voltage to the PN diode, wherein N-type and P-type semiconductors of the PN diode are doped at high concentrations and the doping concentration of the N-type semiconductor is higher than or equal to that of the P-type semiconductor.

Abstract translation: 提供了使用PN二极管的光电装置和包括光电装置的硅集成电路（IC）。 光电装置包括：基板; 以及在所述衬底上形成为PN二极管的光波导，其中所述PN二极管的结界面沿光前进的方向形成; 以及向PN二极管施加反向电压的电极，其中PN二极管的N型和P型半导体以高浓度掺杂，并且N型半导体的掺杂浓度高于或等于P 型半导体。

公开(公告)号：US20090261383A1

公开(公告)日：2009-10-22

申请号：US12441381

申请日：2007-08-17

Applicant: Bongki Mheen ,  Jeong-Woo Park ,  Hyun-Soo Kim ,  Gyungock Kim

Inventor： Bongki Mheen ,  Jeong-Woo Park ,  Hyun-Soo Kim ,  Gyungock Kim

IPC: H01L29/80

CPC classification number: G02F1/025 ,  G02F1/2257 ,  H01L33/0037

Abstract: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.

Abstract translation: 提供了具有应变埋入通道区域的光学装置。 该光学器件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在栅极绝缘层上的与第一导电类型相反的第二导电类型的栅极; 形成在所述半导体衬底下的高密度掺杂剂扩散区，并且掺杂有比所述半导体衬底更高密度的第一导电型掺杂剂; 由半导体材料形成的应变掩埋沟道区域，具有与形成半导体衬底的材料不同的晶格参数，并且在栅极绝缘层和半导体衬底之间延伸以接触高密度掺杂剂扩散区域; 以及形成在栅绝缘层和应变埋入沟道区之间的半导体盖层。

公开(公告)号：US20090140429A1

公开(公告)日：2009-06-04

申请号：US12292827

申请日：2008-11-26

Applicant: Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

Inventor： Kyu-Ha Lee ,  Cha-Je Jo ,  Jeong-Woo Park

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract translation: 一种制造半导体器件的金属互连的方法包括：形成具有至少一个沟槽的基底层，所述至少一个沟槽具有开放的上部，在所述至少一个沟槽中形成第一金属层，形成种子金属层 在所述至少一个沟槽中的所述第一金属层上，所述籽晶金属层仅在所述至少一个沟槽的底表面上，并且形成从种子金属层生长以填充所述至少一个沟槽的金属图案。

公开(公告)号：US20090001398A1

公开(公告)日：2009-01-01

申请号：US12155877

申请日：2008-06-11

Applicant: Ho Young Song ,  Dong Yu Kim ,  Jeong Woo Park ,  Yong Chun Kim ,  Hyung Ky Back

Inventor： Ho Young Song ,  Dong Yu Kim ,  Jeong Woo Park ,  Yong Chun Kim ,  Hyung Ky Back

IPC: H01L33/00

CPC classification number: H01L33/12 ,  H01L33/16 ,  H01L33/22

Abstract: There are provided a semiconductor light emitting device that can be manufactured by a simple process and has excellent light extraction efficiency and a method of manufacturing a semiconductor light emitting device that has high reproducibility and high throughput. A semiconductor light emitting device having a substrate and a lamination in which a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are sequentially laminated onto the substrate according to an aspect of the invention includes a silica particle layer; and an uneven part formed at a lower part of the silica particle layer.

Abstract translation: 提供了可以通过简单的工艺制造并且具有优异的光提取效率的半导体发光器件和制造具有高再现性和高生产量的半导体发光器件的方法。 根据本发明的一个方面，具有基板和叠层体的半导体发光器件依次层叠在基板上，其中第一导电型半导体层，有源层和第二导电类型半导体层包括二氧化硅颗粒层; 以及形成在二氧化硅粒子层的下部的不平坦部。

公开(公告)号：US20080264676A1

公开(公告)日：2008-10-30

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20080251494A1

公开(公告)日：2008-10-16

申请号：US12078058

申请日：2008-03-26

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

IPC: H01B13/00 ,  C25D5/34

CPC classification number: C25D7/123 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/108

Abstract: A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.

Abstract translation: 公开了一种制造电路板的方法。 该方法可以包括：在层叠在载体上的金属层上形成与电路图案对应关系的释放图案; 将载体堆叠并压制到绝缘层上，其中减震图案面向绝缘层; 通过移除载体将金属层和释放图案转印到绝缘层中; 在所述绝缘层上形成通孔，所述绝缘层中所述金属层被转录到所述绝缘层上; 并通过在其上转印有金属层的绝缘层上进行电镀来填充通孔并在金属层上形成镀层。 由于可以在堆叠在载体上的金属层上形成缓和图案，并且可以将缓冲图案转录到绝缘层中，可以形成高密度电路图案。

公开(公告)号：US20080080803A1

公开(公告)日：2008-04-03

申请号：US11833004

申请日：2007-08-02

Applicant: Jeong Woo PARK ,  Gyungock KIM ,  Hyun Soo KIM ,  Bongki MHEEN

Inventor： Jeong Woo PARK ,  Gyungock KIM ,  Hyun Soo KIM ,  Bongki MHEEN

IPC: G02F1/035

CPC classification number: G02F1/025 ,  G02F1/3133 ,  G02F2001/0152 ,  G02F2203/15

Abstract: Provided is a high-speed ring optical modulator based on a silicon semiconductor, having increased optical modulation speed. The high-speed ring optical modulator includes a ring optical waveguide including a portion in which the refractive index varies, that is, a refractive index variation portion, and an optical waveguide having a constant refractive index. The refractive index variation portion comprises a bipolar transistor. Thus carriers can be supplied to and discharged from the refractive index variation portion, through which light is transmitted, at high speed, and thus the optical modulation speed can be increased.

Abstract translation: 提供了一种基于硅半导体的高速环形光调制器，其具有增加的光调制速度。 高速环形光调制器包括环形光波导，其包括折射率变化的部分，即折射率变化部分和具有恒定折射率的光波导。 折射率变化部分包括双极晶体管。 因此，可以高速地将载流子提供给发射光的折射率变化部分放出，从而可以提高光调制速度。