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    HIGHLY SELECTIVE DOPED OXIDE REMOVAL METHOD
    71.
    发明申请
    HIGHLY SELECTIVE DOPED OXIDE REMOVAL METHOD 有权
    高选择性去氧化物去除方法

    公开(公告)号：US20150371866A1

    公开(公告)日：2015-12-24

    申请号：US14309625

    申请日：2014-06-19

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun Chen ,  Zihui Li ,  Nitin K. Ingle ,  Anchuan Wang ,  Shankar Venkataraman

    IPC: H01L21/311 ,  H01L21/02

    CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/70

    Abstract: A method of etching doped silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the doped silicon oxide. The plasmas effluents react with the patterned heterogeneous structures to selectively remove doped silicon oxide.

    Abstract translation: 描述了在图案化的异质结构上蚀刻掺杂的氧化硅的方法，并且包括使用部分远程等离子体激发的气相蚀刻。 远程等离子体激发含氟前体，产生的等离子体流出物流入基板处理区域。 含氢前体，例如 水同时流入基板处理区域而没有等离子体激发。 在衬底处理区域中，等离子体流出物与未掺杂的含氢前体结合，其中组合与掺杂的氧化硅反应。 等离子体流出物与图案化的异质结构反应以选择性地去除掺杂的氧化硅。

    FLASH GATE AIR GAP
    74.
    发明申请
    FLASH GATE AIR GAP 有权
    闪光门空气隙

    公开(公告)号：US20150270366A1

    公开(公告)日：2015-09-24

    申请号：US14222418

    申请日：2014-03-21

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Nitin K. Ingle

    IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L29/788

    CPC classification number: H01L29/515 ,  H01J37/32357 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/788

    Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

    Abstract translation: 对具有气隙的闪存单元描述闪存单元和形成方法，电子可通过该空隙来改变浮动栅极的电荷状态。 最初沉积一个虚拟栅极，并在该虚拟栅极上沉积多晶硅栅极。 然后在有源区域，伪栅极和多晶硅的侧面上沉积氧化硅膜。 氧化硅膜将多晶硅保持就位，同时选择性地蚀刻掉虚拟栅极。 伪栅极可以被掺杂以增加蚀刻速率。 以前，使用氧化硅作为电子通过电介质势垒来对浮栅（多晶硅）进行充电和放电。 在介质屏障中消除材料减少了在使用过程中累积陷阱电荷的趋势，并增加了闪存器件的使用寿命。

    DOPANT ETCH SELECTIVITY CONTROL
    76.
    发明申请
    DOPANT ETCH SELECTIVITY CONTROL 有权
    DOPANT ETCH选择性控制

    公开(公告)号：US20150170920A1

    公开(公告)日：2015-06-18

    申请号：US14230590

    申请日：2014-03-31

    Applicant: Applied Materials, Inc.

    Inventor： Vinod R. Purayath ,  Anchuan Wang ,  Nitin K. Ingle

    IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/3065

    CPC classification number: H01L21/28273 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/32137

    Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

    Abstract translation: 描述了以两种不同蚀刻速率蚀刻两个掺杂硅部分的方法。 当两者都暴露并存在于相同的衬底上时，可以比p型硅部分蚀刻n型硅部分。 n型硅部分可以掺杂磷，并且p型硅部分可以掺杂硼。 在一个示例中，n型硅部分是单晶硅，p型硅部分是多晶硅（即多晶硅）。 p型硅部分可以是闪存单元中的多晶硅浮动栅极，并且可以位于栅极氧化硅的上方，栅极氧化硅又位于n型有源区单晶硅部分之上。 n型有源区硅部分的额外修整可以减少使用期间被捕获的电荷的累积并且增加闪存器件的寿命。

    ETCH SUPPRESSION WITH GERMANIUM
    77.
    发明申请
    ETCH SUPPRESSION WITH GERMANIUM 有权
    与德国的灭活剂

    公开(公告)号：US20150126039A1

    公开(公告)日：2015-05-07

    申请号：US14269544

    申请日：2014-05-05

    Applicant: Applied Materials, Inc.

    Inventor： Mikhail Korolik ,  Nitin K. Ingle ,  Jingchun Zhang ,  Anchuan Wang ,  Jie Liu

    IPC: H01L21/3065

    CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J2237/3346

    Abstract: Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon. The plasmas effluents react with exposed surfaces and selectively remove silicon while very slowly removing other exposed materials. The methods are useful for removing Si(1-X)GeX faster than Si(1-Y)GeY, for X

    Abstract translation: 描述了相对于硅锗选择性地蚀刻硅的方法。 该方法包括使用由含氟前体和含氢前体形成的等离子体流出物的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域，其中等离子体流出物与硅反应。 等离子体流出物与暴露的表面反应并选择性地去除硅，同时非常缓慢地除去其它暴露的材料。 对于X

    Low shrinkage dielectric films
    78.
    发明授权
    Low shrinkage dielectric films 有权
    低收缩介电膜

    公开(公告)号：US09018108B2

    公开(公告)日：2015-04-28

    申请号：US13834333

    申请日：2013-03-15

    Applicant: Applied Materials, Inc.

    Inventor： Sukwon Hong ,  Toan Tran ,  Abhijit Mallick ,  Jingmei Liang ,  Nitin K. Ingle

    IPC: H01L21/31 ,  H01L21/02 ,  C23C16/56 ,  C23C16/452 ,  C23C16/34

    CPC classification number: H01L21/02274 ,  C23C16/045 ,  C23C16/345 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/0234

    Abstract: Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.

    Abstract translation: 描述了在基板上形成电介质层的方法，并且可以包括将第一前体引入到与衬底处理室的衬底处理区域流体耦合的远程等离子体区域中。等离子体可以形成在远程等离子体区域中以产生等离子体流出物 。 等离子体流出物可以被引导到基板处理区域中。 可以将含硅前体引入衬底处理区域，并且含硅前体可以包括至少一个硅 - 硅键。 等离子体流出物和含硅前体可以在处理区域中反应以形成当在基底上形成时最初可流动的硅基电介质层。

    Selective etch of silicon nitride
    79.
    发明授权
    Selective etch of silicon nitride 有权
    氮化硅的选择性蚀刻

    公开(公告)号：US08956980B1

    公开(公告)日：2015-02-17

    申请号：US14089182

    申请日：2013-11-25

    Applicant: Applied Materials, Inc.

    Inventor： Zhijun Chen ,  Zihui Li ,  Anchuan Wang ,  Nitin K. Ingle ,  Shankar Venkataraman

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

    CPC classification number: H01L21/02205 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116

    Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.

    Abstract translation: 描述了在图案化的异质结构上蚀刻氮化硅的方法，并且包括由含氟前体和含氮和氧的前体形成的远程等离子体蚀刻。 来自两个远程等离子体的等离子体流出物流入基板处理区域，其中等离子体流出物与氮化硅反应。 等离子体流出物与图案化的异质结构反应以选择性地去除氮化硅，同时非常缓慢地除去硅，例如多晶硅。 氮化硅选择性部分取决于使用可能是串联或并联的不同（但可能重叠的）等离子体途径引入含氟前体和含氮和氧的前体。

    Tungsten oxide processing
    80.
    发明授权
    Tungsten oxide processing 有权
    氧化钨加工

    公开(公告)号：US08951429B1

    公开(公告)日：2015-02-10

    申请号：US14136200

    申请日：2013-12-20

    Applicant: Applied Materials, Inc.

    Inventor： Jie Liu ,  Xikun Wang ,  Seung Park ,  Mikhail Korolik ,  Anchuan Wang ,  Nitin K. Ingle

    IPC: B44C1/22 ,  C23F1/00 ,  C23F3/00 ,  H01J37/32

    CPC classification number: H01J37/32449 ,  H01J37/32357 ,  H01L21/31122

    Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor in combination with ammonia (NH3). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. Increasing a flow of ammonia during the process removes a typical skin of tungsten oxide having higher oxidation coordination number first and then selectively etching lower oxidation tungsten oxide. In some embodiments, the tungsten oxide etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

    Abstract translation: 描述了相对于钨，氧化硅，氮化硅和/或氮化钛选择性地蚀刻氧化钨的方法。 这些方法包括使用由含氟前体与氨（NH 3）组合形成的等离子体流出物的远程等离子体蚀刻。 来自远程等离子体的等离子体流出物流入基板处理区域，其中等离子体流出物与氧化钨反应。 等离子体流出物与暴露的表面反应并选择性地去除氧化钨，同时非常缓慢地除去其它暴露的材料。 在该过程中增加氨的流动首先除去具有较高氧化配位数的氧化钨的典型表面，然后选择性地蚀刻较低的氧化氧化钨。 在一些实施例中，氧化钨蚀刻选择性部分地来自位于远程等离子体和基板处理区域之间的离子抑制元件的存在。

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