公开(公告)号：US20120301706A1

公开(公告)日：2012-11-29

申请号：US13568808

申请日：2012-08-07

申请人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

发明人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

IPC分类号： C23C16/50 ,  B32B3/26

CPC分类号： C23C16/45536 ,  C23C16/36 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/3141 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24999

摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.

摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。

公开(公告)号：US20120282784A1

公开(公告)日：2012-11-08

申请号：US13553264

申请日：2012-07-19

申请人： Sampath Purushothaman ,  Geraud Jean-Michel Dubois ,  Teddie P. Magbitang ,  Willi Volksen ,  Theo J. Frot

发明人： Sampath Purushothaman ,  Geraud Jean-Michel Dubois ,  Teddie P. Magbitang ,  Willi Volksen ,  Theo J. Frot

IPC分类号： H01L21/3105

CPC分类号： H01L21/3105 ,  H01L21/02203 ,  H01L21/7682 ,  H01L2221/1047

摘要： In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.

摘要翻译： 在一个示例性实施例中，一种方法包括：提供具有覆盖衬底的第一层的结构，其中第一层包括具有多个孔的电介质材料; 将填充材料施加到第一层的暴露表面; 将结构加热到第一温度以使填充材料均匀地填充多个孔; 在填充所述多个孔之后，在所述结构上执行至少一个处理; 并且在执行所述至少一个处理之后，通过将所述结构加热至第二温度以分解所述填充材料，从所述多个孔中除去所述填充材料。

公开(公告)号：US20120261823A1

公开(公告)日：2012-10-18

申请号：US13531518

申请日：2012-06-23

申请人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew E. Colburn ,  Satya V. Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US20120233510A1

公开(公告)日：2012-09-13

申请号：US13043749

申请日：2011-03-09

申请人： Evan G. Colgan ,  Monty M. Denneau ,  Kimberley A. Kelly ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Evan G. Colgan ,  Monty M. Denneau ,  Kimberley A. Kelly ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： G11C5/02 ,  G06F11/07

CPC分类号： G11C5/025 ,  G11C5/063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.

摘要翻译： 芯片堆叠结构包括具有有源器件表面的逻辑芯片和垂直对齐的存储器单元的存储器片，使得存储器片的表面垂直于逻辑芯片的有源器件表面定向。 芯片堆叠结构还包括在存储器片的上表面上图案化的布线，布线将存储器片的存储器引线电连接到对应于逻辑芯片的逻辑电路连接的逻辑栅极。

公开(公告)号：US08093099B2

公开(公告)日：2012-01-10

申请号：US12763596

申请日：2010-04-20

申请人： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

发明人： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongqing Yu

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/83 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/105 ,  H01L2221/68377 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/83121 ,  H01L2224/83141 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/01028

摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

摘要翻译： 三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。 形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。 通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

公开(公告)号：US07989291B2

公开(公告)日：2011-08-02

申请号：US12712369

申请日：2010-02-25

申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC分类号： H01L29/72

CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。

公开(公告)号：US07947907B2

公开(公告)日：2011-05-24

申请号：US12098895

申请日：2008-04-07

申请人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardos Standaert ,  Xiao Hu Liu

发明人： Matthew Earl Colburn ,  Ricardo Alves Donaton ,  Conal E Murray ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thedorus Eduardos Standaert ,  Xiao Hu Liu

IPC分类号： H05K1/03

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like.

摘要翻译： 一种电子结构，其包括具有介电层的介质层和介电层上方的介电阻挡层中的至少一个金属互连结构的基板，以及涂覆有自组装层的多层硬掩模堆叠，其中自组装 层是纳米尺度和/或微细孔隙的图案，其在介电阻挡层中产生并且进入与金属互连结构相邻的电介质层中，以在其中的介电阻挡层和电介质层中产生柱。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。

公开(公告)号：US07863150B2

公开(公告)日：2011-01-04

申请号：US11518773

申请日：2006-09-11

申请人： Matthew Earl Colburn ,  Daniel C. Edelstein ,  Satya Venkata Nitta ,  Sampath Purushothaman ,  Shom Ponth

发明人： Matthew Earl Colburn ,  Daniel C. Edelstein ,  Satya Venkata Nitta ,  Sampath Purushothaman ,  Shom Ponth

IPC分类号： H01L21/76

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

摘要翻译： 在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

公开(公告)号：US20100314767A1

公开(公告)日：2010-12-16

申请号：US12485366

申请日：2009-06-16

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。

公开(公告)号：US20100314711A1

公开(公告)日：2010-12-16

申请号：US12194211

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L27/12 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。 提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。 第一有源电路层晶片比另一个晶片低成本。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。