公开(公告)号：US10886196B2

公开(公告)日：2021-01-05

申请号：US16371635

申请日：2019-04-01

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/36 ,  H01L23/42 ,  H01L23/498

Abstract: Semiconductor devices having a conductive via and methods of forming the same are described herein. As an example, a semiconductor devices may include a conductive via formed in a substrate material, a barrier material, a first dielectric material on the barrier material, a coupling material formed on the substrate material and on at least a portion of the dielectric material, a second dielectric material formed on the coupling material, and an interconnect formed on the conductive via.

公开(公告)号：US10297577B2

公开(公告)日：2019-05-21

申请号：US15693750

申请日：2017-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/40 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/18 ,  H01L23/538

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US20190074194A1

公开(公告)日：2019-03-07

申请号：US15847687

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Dale Arnold

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  C23C18/32

CPC classification number: H01L21/4846 ,  C23C18/32 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/16237

Abstract: Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least include a substrate, a contact on the substrate, and a mask layer formed on the substrate and at least a portion of the contact. The mask layer may also include an opening formed therein, with the opening having a discontinuous profile from a top surface of the mask layer to the contact.

公开(公告)号：US20190006323A1

公开(公告)日：2019-01-03

申请号：US16122280

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US10163830B2

公开(公告)日：2018-12-25

申请号：US15344893

申请日：2016-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US20180219002A1

公开(公告)日：2018-08-02

申请号：US15938305

申请日：2018-03-28

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/427 ,  H01L23/46 ,  H01L23/473 ,  H01L23/42

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

公开(公告)号：US20180190620A1

公开(公告)日：2018-07-05

申请号：US15905086

申请日：2018-02-26

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

公开(公告)号：US20180190571A1

公开(公告)日：2018-07-05

申请号：US15910136

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/48 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02125 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

公开(公告)号：US20180040592A1

公开(公告)日：2018-02-08

申请号：US15788094

申请日：2017-10-19

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/075 ,  H01L23/40 ,  H01L23/00 ,  H01L25/04 ,  H01L23/498 ,  H01L23/34 ,  H01L25/00 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

公开(公告)号：US20170365584A1

公开(公告)日：2017-12-21

申请号：US15693750

申请日：2017-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/367 ,  H01L23/40 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/3738 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2224/83

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.