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114 条记录 (耗时 0.037 秒)

    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
    71.
    发明授权
    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
    包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例

    公开(公告)号：US07723226B2

    公开(公告)日：2010-05-25

    申请号：US11654427

    申请日：2007-01-17

    申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

    摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

    Method for modulating stresses of a contact etch stop layer
    73.
    发明授权
    Method for modulating stresses of a contact etch stop layer 有权
    用于调节接触蚀刻停止层的应力的方法

    公开(公告)号：US07629273B2

    公开(公告)日：2009-12-08

    申请号：US11523674

    申请日：2006-09-19

    申请人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    发明人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3105 ,  H01L21/823807 ,  H01L29/7843

    摘要： A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

    摘要翻译： 一种形成半导体结构的方法包括提供包括第一器件区域的衬底，在第一器件区域中形成金属氧化物半导体（MOS）器件，在MOS器件上形成应力层，并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线（UV）固化，激光固化，电子束固化及其组合组成的组。

    Metal structure with sidewall passivation and method
    75.
    发明授权
    Metal structure with sidewall passivation and method 有权
    金属结构与侧壁钝化和方法

    公开(公告)号：US07446047B2

    公开(公告)日：2008-11-04

    申请号：US11061350

    申请日：2005-02-18

    申请人： Minghsing Tsai ,  Yung-Cheng Lu

    发明人： Minghsing Tsai ,  Yung-Cheng Lu

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76834 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835

    摘要： A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.

    摘要翻译： 公开了钝化金属结构和形成金属结构的方法。 根据一个实施例，图案化的金属结构，例如导电线，形成在基板上。 铜线由铜线之间的聚合物衬垫和填充导电线之间的空间的低k电介质钝化。 聚合物衬垫优选通过电接枝沉积在导电线的侧壁上。 聚合物衬垫也可以用于根据第二实施例的镶嵌工艺中。

    Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip
    77.
    发明授权
    Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip 有权
    用于在集成电路芯片中的导电线和蚀刻停止层之间的粘附改善的胶层

    公开(公告)号：US07405481B2

    公开(公告)日：2008-07-29

    申请号：US11004065

    申请日：2004-12-03

    申请人： Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

    发明人： Keng-Chu Lin ,  Yung-Cheng Lu ,  Shwang-Ming Cheng

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. The glue layer is formed of a non-oxygen-containing material capable of providing an oxygen barrier over the conductive line. The glue layer has a hardness greater than that of the conductive line. The glue layer preferably has a thickness between about 15 angstroms and about 75 angstroms. The etch stop layer is formed on the glue layer. The etch stop layer has a hardness greater than that of the glue layer. A second IMD layer is formed on the etch stop layer. The etch stop layer and/or the second IMD layer may be formed with a material comprising oxygen without oxidizing the conductive line.

    摘要翻译： 在集成电路芯片中，在第一IMD层中形成导线。 导电线由暴露于含氧物质时易于形成氧化物的导电线材料形成。 在导电线上形成胶层。 胶层由能够在导电线上提供氧阻隔的非含氧材料形成。 胶层的硬度大于导电线的硬度。 胶层优选地具有在约15埃至约75埃之间的厚度。 蚀刻停止层形成在胶层上。 蚀刻停止层的硬度大于胶层的硬度。 在蚀刻停止层上形成第二IMD层。 蚀刻停止层和/或第二IMD层可以由包含氧的材料形成而不氧化导电线。

    Method for modulating stresses of a contact etch stop layer
    78.
    发明申请
    Method for modulating stresses of a contact etch stop layer 有权
    用于调节接触蚀刻停止层的应力的方法

    公开(公告)号：US20080085607A1

    公开(公告)日：2008-04-10

    申请号：US11523674

    申请日：2006-09-19

    申请人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    发明人： Chen-Hua Yu ,  Hung Chun Tsai ,  Hui-Lin Chang ,  Ting-Yu Shen ,  Yung-Cheng Lu

    IPC分类号： H01L21/31

    CPC分类号： H01L21/3105 ,  H01L21/823807 ,  H01L29/7843

    摘要： A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

    摘要翻译： 一种形成半导体结构的方法包括提供包括第一器件区域的衬底，在第一器件区域中形成金属氧化物半导体（MOS）器件，在MOS器件上形成应力层，并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线（UV）固化，激光固化，电子束固化及其组合组成的组。

    Methods for improving uniformity of cap layers
    79.
    发明申请
    Methods for improving uniformity of cap layers 有权
    改善盖层均匀性的方法

    公开(公告)号：US20080032472A1

    公开(公告)日：2008-02-07

    申请号：US11524000

    申请日：2006-09-20

    申请人： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

    发明人： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/76826

    摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

    摘要翻译： 形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。