公开(公告)号：US20160091532A1

公开(公告)日：2016-03-31

申请号：US14498291

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Chin-Kwan Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Seung Hyuk Kang

IPC: G01R1/073 ,  H01L21/66 ,  H01L21/48 ,  G01R31/28

CPC classification number: G01R1/0735 ,  G01R1/07378 ,  G01R31/2887 ,  H01L21/4853 ,  H01L21/4857 ,  H01L22/30

Abstract: Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC.

Abstract translation: 公开了具有至少一个用于集成电路（IC）凸点电气测试的导电接触柱的柔性膜电测基板，以及相关方法和测试装置。 电测基板的背面结构包括柔性介电膜结构。 通过制造工艺，在设置在柔性电介质膜结构的前侧的导电焊盘上形成一个或多个细间距导电耦合柱。 将柔性电介质膜结构中的导电耦合柱的第一间距设置成与IC中的一个或多个凸起的第二间距相同或基本相同，例如模具或插入件（例如，40（ 40微米（μm）以下）。 这允许导电耦合柱在电测试期间被放置成与IC的至少一个凸点相接触，以电IC测试。

公开(公告)号：US09275876B2

公开(公告)日：2016-03-01

申请号：US14042140

申请日：2013-09-30

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Changhan Hobie Yun

IPC: H01L21/00 ,  H01L21/52 ,  H01L21/48 ,  H01L23/13 ,  H01L49/02 ,  H01L23/16 ,  H01L23/04

CPC classification number: H01L21/52 ,  H01L21/4817 ,  H01L23/04 ,  H01L23/13 ,  H01L23/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Abstract translation: 用于防止半导体封装中的半导体衬底翘曲的系统和方法。 连续或不间断的加强结构设计有凹槽，使得诸如高密度电容器的无源部件容纳在凹槽内。 具有凹槽的加强结构使用各向异性导电膜（ACF）或各向异性导电膏（ACP）附着到半导体衬底上。 具有凹槽的加强结构围绕可形成在半导体衬底上的一个或多个半导体器件。 具有凹槽的加强结构不延伸超过半导体衬底的水平边界。

公开(公告)号：US20160049378A1

公开(公告)日：2016-02-18

申请号：US14462265

申请日：2014-08-18

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Hong Bok We ,  Dong Wook Kim ,  Kyu-Pyung Hwang

IPC: H01L23/00 ,  H01L23/367

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H05K1/0207 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract translation: 本文提供了一种集成器件，其包括衬底，管芯，位于衬底和管芯之间的散热层和被配置为将管芯耦合到散热层的第一互连。 散热层可以被配置成为接地信号提供电路径。 第一互连可以被进一步配置成将热量从管芯传导到散热层。 集成器件还可以包括配置成将管芯耦合到衬底的第二互连。 第二互连可以被进一步配置为在管芯和衬底之间传导功率信号。 集成器件还可以包括位于散热层和衬底之间的介电层，以及位于管芯和散热层之间的阻焊层。

公开(公告)号：US20150237732A1

公开(公告)日：2015-08-20

申请号：US14200684

申请日：2014-03-07

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco Velez ,  Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/40 ,  H05K1/03 ,  H05K1/16 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K1/182 ,  H01F17/0006 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/10 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/165 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/10242 ,  H05K2201/10984 ,  Y10T29/49165

Abstract: A low-profile passive-on-package is provided that includes a plurality of recesses that receive corresponding interconnects. Because of the receipt of the interconnects in the recesses, the passive-on-package has a height that is less than a sum of a thickness for the substrate and an interconnect height or diameter.

Abstract translation: 提供了一种低调无源封装，其包括接收相应互连的多个凹槽。 由于在凹槽中接收到互连，所以被动封装的高度小于衬底的厚度和互连高度或直径的总和。

公开(公告)号：US09093295B2

公开(公告)日：2015-07-28

申请号：US14079503

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Changhan Hobie Yun

IPC: H01L21/02 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G2/06 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/30 ,  H01G4/306 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L27/0805 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16267 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/014

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract translation: 提供了一种层叠电容器，其包括多个通孔，其构造成从模具接收互连。

公开(公告)号：US20150146340A1

公开(公告)日：2015-05-28

申请号：US14090589

申请日：2013-11-26

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Kyu-Pyung Hwang ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01G4/30

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12

Abstract: An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer.

Abstract translation: 一种装置包括两端MLCC。 双端MLCC包括导电层，其中导电层包括至少一个槽。 该装置还可以包括第二导电层，其包括至少一个槽和分离两个导电层的绝缘层。 在一个示例中，双端子MLCC的第一（例如，正）端子由第一组板形成，其中第一组中的每个板包括至少一个槽。 双端子MLCC的第二（例如，负极）端子由第二组板形成，其中第二组中的每个板还包括至少一个槽。 第一组板和第二组板被交错，并且每对板由绝缘层分开。

公开(公告)号：US20150130021A1

公开(公告)日：2015-05-14

申请号：US14079488

申请日：2013-11-13

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Xiaonan Zhang ,  Jonghae Kim

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/0053

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

Abstract translation: 一些实施方式提供了一种集成器件（例如，半导体器件），其包括衬底中的衬底和电感器。 在一些实施方案中，电感器是螺线管电感器。 电感器包括一组绕组。 该组绕组具有内周。 该组绕组包括一组互连和一组通孔。 该组互连和一组通孔位于该组绕组的内周边之外。 在一些实施方案中，该组绕组还包括一组捕获垫。 该组互连通过一组捕获垫耦合到该组通孔。 在一些实施方式中，该组绕组具有外周边。 该组焊盘耦合到该组互连件，使得该组焊盘至少部分地位于该组绕组的外周边之外。

公开(公告)号：US20150092314A1

公开(公告)日：2015-04-02

申请号：US14039192

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Mario Francisco Velez ,  Jonghae Kim ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Xiaonan Zhang ,  Ryan David Lane ,  Matthew Michael Nowak

IPC: H01F27/29 ,  H01F41/04 ,  H01F27/40

CPC classification number: H01F27/29 ,  H01F17/0006 ,  H01F27/40 ,  H01F2017/002 ,  H01F2017/0073 ,  Y10T29/4902

Abstract: A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.

Abstract translation: 系统包括耦合到衬底的第一表面的第一连接器。 第一连接器使得系统能够电耦合到衬底外部的第一器件。 该系统包括耦合到基板的第二表面的第二连接器。 该系统还包括从第一表面延伸穿过基底的多个导电通孔到第二表面。 多个导电通孔围绕第一连接器和第二连接器。 多个导电通孔电耦合在一起以形成环形电感器。 环形电感器的第一引线电耦合到第一连接器。 环形电感器的第二引线电耦合到第二连接器。