公开(公告)号：US20090315190A1

公开(公告)日：2009-12-24

申请号：US12306987

申请日：2007-06-29

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H01L23/538 ,  H05K1/11 ,  H01L21/60 ,  H01L21/31

CPC分类号： H05K3/205 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/423 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

摘要翻译： 布线基板具有绝缘层，多个布线层以通过绝缘层彼此绝缘的方式形成，以及形成在绝缘层中以连接布线层的多个通孔。 在布线层中，形成在绝缘层的一个表面上的表面布线层包括从一个表面露出的第一金属膜和嵌入在绝缘层中并叠放在第一金属膜上的第二金属膜。 第一金属膜的边缘沿着第二金属膜扩展的方向从第二金属膜的边缘突出。 通过以这种方式设计嵌入在绝缘层中的布线层的形状，可以获得在制造过程中可以有效地防止侧蚀刻的高可靠性布线板，并且可以适应电线的小型化和高密度封装 。

公开(公告)号：US20080303136A1

公开(公告)日：2008-12-11

申请号：US12135355

申请日：2008-06-09

申请人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

发明人： Kentaro Mori ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Masaya Kawano ,  Takehiko Maeda ,  Kouji Soejima

IPC分类号： H01L23/15 ,  H01L21/58

CPC分类号： H01L21/6835 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10S438/977 ,  H01L2924/00

摘要： A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

摘要翻译： 透明板位于设置有定位标记的支撑板上，并且设置有释放材料。 然后将半导体元件定位成使得电极元件面向上，然后移除支撑板。 然后在剥离材料上形成绝缘树脂以覆盖半导体元件; 然后形成通孔，布线层，绝缘层，外部端子和阻焊剂。 然后透明板通过使用释放材料从半导体器件剥离。 因此，可以高精度地安装芯片，在制造过程中不需要在将芯片安装在基板上时提供定位标记，并且可以容易地去除基板。 结果，可以以低成本制造具有高密度和薄型的半导体器件。

公开(公告)号：US20080136020A1

公开(公告)日：2008-06-12

申请号：US11790155

申请日：2007-04-24

申请人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Koji Soejima ,  Yoichiro Kurita ,  Masaya Kawano ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

摘要翻译： 第一电子电路部件和第二电子电路部件分别经由第一焊料和第二焊料电连接到导电部件。 导电构件形成在树脂膜中。 导电构件被构造成包含第二扩散阻挡金属膜。 第二扩散阻挡金属膜防止第二焊料的扩散。 在导电构件和第一焊料之间设置有第一扩散阻挡金属膜。 第一扩散阻挡金属膜防止第一焊料的扩散。 在树脂膜的第一表面和导电部件上形成粘接金属膜，以与树脂膜和导电部件接触。 粘合金属膜比第一焊料和第一扩散阻挡金属膜中的任一种具有比树脂膜更强的粘附性。

公开(公告)号：US07348673B2

公开(公告)日：2008-03-25

申请号：US11180729

申请日：2005-07-14

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Hirokazu Honda ,  Koji Soejima ,  Shinichi Miyazaki

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Hirokazu Honda ,  Koji Soejima ,  Shinichi Miyazaki

IPC分类号： H01L23/48

CPC分类号： H01L23/528 ,  H01L23/3114 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C. is not more than that of the second insulating layers, each of the third wiring layers and each of the third insulating layers being alternately laminated.

摘要翻译： 在半导体基板上形成包括第一布线层和第一绝缘层的微小布线结构部分，其中第一布线层和每个第一绝缘层交替层叠。 第一巨型布线结构部分形成在微小布线结构部分上，并且第一巨大的布线结构部分通过在微小的布线结构部分上依次形成，按照以下顺序形成包括第二布线层的第一巨大布线部分具有 其中第二布线层和每个第二布线层交替层叠的第一布线层和第二绝缘层的厚度的两倍或更多的厚度，以及包括第三布线层的第二巨大布线结构部分的厚度为 第一布线层的厚度的2倍以上，25℃下的弹性模量不大于第2绝缘层的弹性模量的第3绝缘层，第3布线层和第3绝缘层 交替层压。

公开(公告)号：US20080012140A1

公开(公告)日：2008-01-17

申请号：US11822599

申请日：2007-07-09

申请人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H05K1/0271 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09018 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.

摘要翻译： 布线基板包括基底绝缘膜，形成在基底绝缘膜的上表面侧上的第一互连，设置在形成在基底绝缘膜中的通孔中的通孔导体，以及设置在基底绝缘膜的底面侧的第二互连 基底绝缘膜，第二互连件经由通孔导体连接到第一互连件。 布线基板包括分割的基板单元区域，其中形成有第一互连，通孔导体和第二互连。 布线基板包括在基底绝缘膜上的翘曲控制图案，并且具有翘曲形状，使得当布线基板静止在水平板上时，基板的平面的每一侧的至少中心部分 接触水平板，其侧面的两端被凸起，其中每个侧面沿着垂直于基板的平面表面中的第一方向的第二方向延伸。

公开(公告)号：US20060283629A1

公开(公告)日：2006-12-21

申请号：US11449673

申请日：2006-06-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H05K1/11 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

摘要翻译： 一种用于安装具有多个布线层的半导体元件或电子元件的布线板，设置在这些布线层之间的绝缘层，以及设置在绝缘层上并将布线层电连接的通孔。 在该布线板中，通过多个相似形状（圆圈）的部分重叠，获得与布线层平行的平面中的通孔的横截面形状。 通过最小化增加密度的障碍物，有效地增加通孔的横截面积，并且通过使通孔的横截面形状成为由通孔形成的形状来防止布线电阻增加，可以在半导体元件中获得稳定的操作 多个类似形状的部分重叠。

公开(公告)号：US20060012048A1

公开(公告)日：2006-01-19

申请号：US11174526

申请日：2005-07-06

申请人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

发明人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

IPC分类号： H01L23/48

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/061 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

摘要翻译： 用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。 电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。 绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去 金属板。

公开(公告)号：US20060012029A1

公开(公告)日：2006-01-19

申请号：US11180729

申请日：2005-07-14

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Hirokazu Honda ,  Koji Soejima ,  Shinichi Miyazaki

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Hirokazu Honda ,  Koji Soejima ,  Shinichi Miyazaki

IPC分类号： H01L23/12

CPC分类号： H01L23/528 ,  H01L23/3114 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C. is not more than that of the second insulating layers, each of the third wiring layers and each of the third insulating layers being alternately laminated.

摘要翻译： 在半导体基板上形成包括第一布线层和第一绝缘层的微小布线结构部分，其中第一布线层和每个第一绝缘层交替层叠。 第一巨型布线结构部分形成在微小布线结构部分上，并且第一巨大的布线结构部分通过在微小的布线结构部分上依次形成，按照以下顺序形成包括第二布线层的第一巨大布线部分具有 其中第二布线层和每个第二布线层交替层叠的第一布线层和第二绝缘层的厚度的两倍或更多的厚度，以及包括第三布线层的第二巨大布线结构部分的厚度为 第一布线层的厚度的2倍以上，25℃下的弹性模量不大于第2绝缘层的弹性模量的第3绝缘层，第3布线层和第3绝缘层 交替层压。

公开(公告)号：US06292352B1

公开(公告)日：2001-09-18

申请号：US09583871

申请日：2000-05-31

申请人： Shintaro Yamamichi

发明人： Shintaro Yamamichi

IPC分类号： H01G406

CPC分类号： H01L28/60 ,  H01L21/76895

摘要： There is provided a thin film capacitor including (a) a semiconductor substrate, (b) an interlayer insulating film formed on the semiconductor substrate, (c) a contact formed throughout the interlayer insulating film such that the contact has an upper surface upwardly projecting, (d) a lower electrode formed on the interlayer insulating film such that the lower electrode covers the upper surface of the contact therewith, (e) a capacitor insulating film covering the lower electrode and the interlayer insulating film therewith, and (f) an upper electrode formed on the capacitor insulating film. The thin film capacitor prevents peeling between the contact and the lower electrode even in an annealing step.

摘要翻译： 提供一种薄膜电容器，其包括：（a）半导体衬底，（b）形成在半导体衬底上的层间绝缘膜，（c）形成在整个层间绝缘膜上的触点，使得触点具有向上突出的上表面， （d）形成在层间绝缘膜上的下电极，使得下电极覆盖其接触的上表面，（e）覆盖下电极和层间绝缘膜的电容器绝缘膜，以及（f） 电极形成在电容绝缘膜上。 即使在退火步骤中，薄膜电容器也防止接触部和下电极之间的剥离。

公开(公告)号：US5847423A

公开(公告)日：1998-12-08

申请号：US883334

申请日：1997-06-26

申请人： Shintaro Yamamichi

发明人： Shintaro Yamamichi

IPC分类号： H01L21/66 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/06 ,  H01L27/108 ,  H01L29/68

CPC分类号： H01L27/1085 ,  H01L27/0676 ,  H01L28/40

摘要： A semiconductor device having thin film capacitors and containing resistance measuring elementsis disclosed. The thin film capacitor comprises a bottom electrode, a high permittivity dielectric, and a top electrode stacked on an interlayer insulation film and at least one of a plurality of contact formed in electrical contact with the substrate at the desired position of an interlayer insulation film formed on a semiconductor substrate. The bottom electrode comprises at least two layers. A resistance measuring element consists of the same materials as those of the thin film capacitor and has the same size as that of the thin film capacitor except that the resistance measuring element comprises a first electrode, the dielectric film of high permittivity, and a second electrode stacked on the interlayer insulation film and at least one of a plurality of contacts other than the above-mentioned contact for the thin film capacitor, and the topmost layer of the first electrode and the second electrode are in contact with each other through the contact provided at a portion of the dielectric film. The resistance value of the bottom electrode of the thin film capacitor is measured using electrical path through the substrate.

摘要翻译： 公开了具有薄膜电容器并且包含电阻测量元件的半导体器件。 薄膜电容器包括底电极，高介电常数电介质和堆叠在层间绝缘膜上的顶电极以及在形成的层间绝缘膜的期望位置处形成与基板电接触的多个接触中的至少一个 在半导体衬底上。 底部电极包括至少两层。 电阻测量元件由与薄膜电容器相同的材料组成，并且具有与薄膜电容器相同的尺寸，除了电阻测量元件包括第一电极，高介电常数的电介质膜和第二电极 堆叠在层间绝缘膜上，并且除了上述用于薄膜电容器的触点之外的多个触点中的至少一个触点以及第一电极和第二电极的最上层通过所提供的触点彼此接触 在电介质膜的一部分。 薄膜电容器的底部电极的电阻值通过基板的电气路径进行测量。