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    Electric connection box
    71.
    发明授权
    Electric connection box 有权
    电接线盒

    公开(公告)号：US06866526B2

    公开(公告)日：2005-03-15

    申请号：US10656322

    申请日：2003-09-08

    Applicant: Norio Ito

    Inventor： Norio Ito

    IPC: H02G3/16 ,  H05K1/02 ,  H01R12/00

    CPC classification number: H05K1/0256 ,  H05K1/0262 ,  H05K2201/0769 ,  H05K2201/09972 ,  H05K2203/1518 ,  H05K2203/159

    Abstract: In an electric connection box constituted by arranging a bus bar circuit board constituted by arranging a plurality of bus bars having at least two kinds of different potentials on an insulating board in a vertical direction, in bus bar arrangement in which the bus bar having low potential and the bus bar having high potential are contiguously installed in a horizontal direction, the bus bar having the low potential is arranged on an upper side of the bus bar having the high potential in the vertical direction.

    Abstract translation: 在通过布置母线条电路板构成的电连接盒中，该汇流条电路板通过在垂直方向上的绝缘板上布置具有至少两种不同电位的多个汇流条而构成，其中母线具有低电位 并且具有高电位的汇流条沿水平方向连续地安装，具有低电位的汇流条被布置在具有高电位的母线的上侧沿垂直方向。

    Coating for silver plated circuits
    72.
    发明授权
    Coating for silver plated circuits 有权
    镀银电路涂层

    公开(公告)号：US06773757B1

    公开(公告)日：2004-08-10

    申请号：US10412932

    申请日：2003-04-14

    Applicant: Ronald Redline ,  David Angelone ,  Steven A. Castaldi ,  Lenora M Toscano

    Inventor： Ronald Redline ,  David Angelone ,  Steven A. Castaldi ,  Lenora M Toscano

    IPC: B05D136

    CPC classification number: C23C18/42 ,  B05D1/18 ,  B05D3/0254 ,  B05D7/14 ,  B05D2202/40 ,  H05K3/244 ,  H05K3/282 ,  H05K2201/0769

    Abstract: A method for enhancing the solderability of a metallic surface is disclosed where the metallic surface is plated with an immersion or electroless silver plate prior to soldering, after which immersion silver plate is treated with an alkaline polymer coating comprising aqueous vinyl polymers, aqueous acrylic polymers, anti-fungal agents and a benzotriazole or benzimidazole compound to produce a deposit that is resistant to electromigration and that provides an anti-tarnish and anti-corrosion coating on the surface.

    Abstract translation: 公开了一种用于增强金属表面的可焊性的方法，其中金属表面在焊接之前镀有浸渍或无电镀银板，然后用含有乙烯基聚合物的水性丙烯酸聚合物的含水聚合物涂层处理浸渍银板， 抗真菌剂和苯并三唑或苯并咪唑化合物，以产生耐电迁移的沉积物，并且在表面上提供抗晦暗和防腐蚀涂层。

    Apparatus and method for reducing electromigration
    73.
    发明申请
    Apparatus and method for reducing electromigration 有权
    减少电迁移的装置和方法

    公开(公告)号：US20040012492A1

    公开(公告)日：2004-01-22

    申请号：US10296881

    申请日：2002-11-27

    Inventor： William John Testin ,  Dale Wayne King

    IPC: G08B029/00

    CPC classification number: G06F3/0202 ,  H03K19/003 ,  H03K19/1731 ,  H03M11/02 ,  H03M11/20 ,  H05K1/0256 ,  H05K1/0262 ,  H05K1/181 ,  H05K3/3421 ,  H05K2201/0769 ,  H05K2201/10212 ,  H05K2201/10689 ,  Y02P70/611

    Abstract: An apparatus and method therefor wherein instead of applying a high bias voltage 100 per cent of the time to leads susceptible to dendrite formation, the bias voltage is switched from a low bias voltage to a high voltage bias mode when the leads (19) are to be read or scanned by a microprocessor (14), and the bias voltage is then switched back to a low bias voltage mode when the lines are not being read, e.g., at other times, thereby greatly reducing the high bias nullonnull time and dramatically reducing the probability of dendrite formation. The reduction of high bias voltage nullonnull time is accomplished by programming the microprocessor (14) to switch the applicable input ports (16) to be output ports when the leads (19) are not to be read. As output ports, the output impedance and output voltage of the microprocessor are low as opposed to a high input impedance when the terminals are input terminals. When the leads are configured as output leads, the voltage division of the microprocessor low output impedance, in combination with a large valued pull-up resistor (12) which provides the high bias voltage when the leads are input leads, makes the voltage bias on the leads low, thus greatly reducing the probability of dendrite formation.

    Abstract translation: 一种装置及其方法，其中，代替将100％的高偏压施加到容易产生枝晶形成的引线上，当引线（19）为（...）时，偏置电压从低偏置电压切换到高电压偏压模式 由微处理器（14）读取或扫描，并且当线路​​未被读取时偏置电压然后被切换回低电压模式，例如在其他时间，从而大大降低了高偏压“开”时间， 显着降低枝晶形成的可能性。 高电压“开”时间的降低是通过对微处理器（14）进行编程来实现的，当引线（19）不被读取时，可将输入端口（16）切换为输出端口。 作为输出端口，当端子是输入端子时，与高输入阻抗相反，微处理器的输出阻抗和输出电压低。 当引线配置为输出引线时，微处理器的低输出阻抗与大值上拉电阻（12）的组合，当引脚是输入引线时，提供高偏置电压，使得电压偏置 引线低，从而大大降低了枝晶形成的概率。

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