公开(公告)号：US12014926B2

公开(公告)日：2024-06-18

申请号：US18123820

申请日：2023-03-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Min Hsiao ,  Chien-Wen Lai ,  Shih-Chun Huang ,  Yung-Sung Yen ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC分类号： H01L21/033 ,  H10B10/00

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H10B10/00

摘要： A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US11997842B2

公开(公告)日：2024-05-28

申请号：US17462066

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Ming-Chih Yew ,  Shu-Shen Yeh ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H10B10/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L25/065

CPC分类号： H10B10/00 ,  H01L21/563 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/02379 ,  H01L2224/32137

摘要： A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

公开(公告)号：US11984445B2

公开(公告)日：2024-05-14

申请号：US18128505

申请日：2023-03-30

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L23/00 ,  H01L27/088

CPC分类号： H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L24/73 ,  H01L27/088 ,  H01L29/66545 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

公开(公告)号：US20240120332A1

公开(公告)日：2024-04-11

申请号：US18128505

申请日：2023-03-30

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20

CPC分类号： H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L24/73 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

公开(公告)号：US20240105490A1

公开(公告)日：2024-03-28

申请号：US18534475

申请日：2023-12-08

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L2924/13062

摘要： 3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells; a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer; a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, memory control circuits for wear leveling.

公开(公告)号：US20240096884A1

公开(公告)日：2024-03-21

申请号：US18521404

申请日：2023-11-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Shao CHENG ,  Chui-Ya PENG ,  Kung-Wei LEE ,  Shin-Yeu TSAI

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/8222 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L27/092 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/8222 ,  H01L21/8238 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0623 ,  H01L29/66234 ,  H01L29/6653 ,  H01L29/66674 ,  H01L29/7801 ,  H10B10/00 ,  H10B20/20

摘要： A method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. The method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.

公开(公告)号：US11923230B1

公开(公告)日：2024-03-05

申请号：US18382468

申请日：2023-10-20

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US11910585B2

公开(公告)日：2024-02-20

申请号：US17873626

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H10B10/00 ,  G06F30/30 ,  G11C11/412

CPC分类号： H10B10/00 ,  G06F30/30 ,  G11C11/412

摘要： Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

公开(公告)号：US11901290B2

公开(公告)日：2024-02-13

申请号：US17149145

申请日：2021-01-14

申请人： Arm Limited

发明人： Rajiv Kumar Sisodia ,  Andy Wangkun Chen

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H10B10/00 ,  H01L23/522 ,  H01L27/092

CPC分类号： H01L23/528 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092 ,  H10B10/00 ,  H10B10/12

摘要： Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.

公开(公告)号：US20240047426A1

公开(公告)日：2024-02-08

申请号：US18358552

申请日：2023-07-25

申请人： Kepler Computing Inc.

发明人： Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh

IPC分类号： H01L25/065 ,  H01L23/525 ,  G06F9/50 ,  H01L23/00 ,  G11C7/10 ,  G11C11/419 ,  H10B10/00

CPC分类号： H01L25/0657 ,  H01L23/525 ,  G06F9/5077 ,  H01L24/73 ,  G11C7/1006 ,  G11C11/419 ,  H10B10/00 ,  H01L2224/32145

摘要： Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.