公开(公告)号：US08530639B2

公开(公告)日：2013-09-10

申请号：US12448134

申请日：2007-12-11

Applicant: Jong-Hoon Kim ,  Min Kim ,  Hae-Joon Park ,  Han Oh Park

Inventor： Jong-Hoon Kim ,  Min Kim ,  Hae-Joon Park ,  Han Oh Park

IPC: C07H21/00

CPC classification number: C07H21/00 ,  C12N15/1003

Abstract: A method for isolating a nucleic acid from a biological sample includes applying particulate matter to promote co-aggregation and co-precipitation of insoluble aggregate by directly adding to the biological sample, adding to the biological sample in admixture with a cell lysis buffer, adding to the biological sample treated with a cell lysis buffer, adding to cell lysates in admixture with a buffer for forming denatured protein aggregate; or adding to cell lysates comprising the formed denatured protein aggregate. The particulate matter is selected from the group consisting of a material formed from an element of Ag, Fe, Ti, Al, Sn, Si, Cu, Mo, Ni, W or Zn, an oxide, a carbide, a nitride, a boride and a silicide thereof, and a mixture thereof, a polymer selected from PMMA (Poly Methyl MethAcrylate), polyethylene or polyurethane; and a mixture thereof. The insoluble aggregate comprises denatured protein aggregate and cell debris.

Abstract translation: 从生物样品中分离核酸的方法包括通过直接添加到生物样品中来加入颗粒物质以促进不溶性聚集体的共聚和共沉淀，将生物样品与细胞裂解缓冲液混合，加入到 用细胞裂解缓冲液处理生物样品，加入细胞裂解物与缓冲液混合以形成变性蛋白质聚集体; 或加入包含形成的变性蛋白质聚集体的细胞裂解物。 颗粒物质选自由Ag，Fe，Ti，Al，Sn，Si，Cu，Mo，Ni，W或Zn的元素形成的材料，氧化物，碳化物，氮化物，硼化物 及其硅化物及其混合物，选自PMMA（聚甲基丙烯酸甲酯），聚乙烯或聚氨酯的聚合物; 及其混合物。 不溶性聚集体包含变性蛋白质聚集体和细胞碎片。

公开(公告)号：US08462097B2

公开(公告)日：2013-06-11

申请号：US12603764

申请日：2009-10-22

Applicant: Kyung-Wook Kim ,  Jong-Hoon Kim

Inventor： Kyung-Wook Kim ,  Jong-Hoon Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G11C19/184 ,  H01L27/1288

Abstract: A gate drive circuit includes a shift register having stages connected to each other in series. An (m)-th stage (‘m’ is a natural number) includes an output part, a discharging part, a first holding part and a second holding part. The output part outputs the first clock signal as a gate signal in response to a first clock signal provided from an external device and discharges the gate signal in response to a second input signal. The output part includes a first transistor having a first channel length. The discharging part discharges a signal of the first node to the second voltage level. The first holding part maintains a signal of the first node at a level of the gate signal, and is discharged to the second voltage level. The first holding part includes a second transistor having a second channel length that is longer than the first channel length. The second holding part maintains a signal of the first node at a level of the second voltage level.

Abstract translation: 栅极驱动电路包括具有彼此串联连接的级的移位寄存器。 第（m）级（“m”是自然数）包括输出部分，排出部分，第一保持部分和第二保持部分。 输出部分响应于从外部设备提供的第一时钟信号而输出第一时钟信号作为门信号，并响应于第二输入信号而放电门信号。 输出部分包括具有第一通道长度的第一晶体管。 放电部分将第一节点的信号放电到第二电压电平。 第一保持部件将第一节点的信号保持在栅极信号的电平，并且被放电到第二电压电平。 第一保持部分包括具有比第一通道长度更长的第二通道长度的第二晶体管。 第二保持部将第一节点的信号维持在第二电压电平的电平。

公开(公告)号：US08395245B2

公开(公告)日：2013-03-12

申请号：US11953967

申请日：2007-12-11

Applicant: Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

Inventor： Jong Hoon Kim ,  Min Suk Suh ,  Seong Cheol Kim ,  Seung Taek Yang ,  Seung Hyun Lee

IPC: H01L23/495

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

Abstract: A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

Abstract translation: 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US20130043191A1

公开(公告)日：2013-02-21

申请号：US13643395

申请日：2011-04-29

Applicant: Han-oh Park ,  Jong-kab Kim ,  Yang-won Lee ,  Jong-hoon Kim

Inventor： Han-oh Park ,  Jong-kab Kim ,  Yang-won Lee ,  Jong-hoon Kim

IPC: B03C1/02

CPC classification number: C12M33/06 ,  C12N15/1003

Abstract: Disclosed is an automatic purification apparatus for isolating target substances from multiple biological samples, and more particularly to an automatic biological sample purification apparatus equipped with a magnetic field applying part, in which the magnetic field applying part for purifying biological samples and a heating part are integrally formed with each other so as to be movable up and down.Further, disclosed is a method of extracting a target substance from the biological sample using the automatic biological sample purification apparatus equipped with the magnetic field applying part.

Abstract translation: 公开了一种用于从多个生物样品中分离目标物质的自动净化装置，更具体地，涉及一种具有磁场施加部的自动生物样品净化装置，其中用于纯化生物样品的磁场施加部和加热部一体化 彼此形成为可上下移动。 此外，公开了使用配备有磁场施加部的自动生物样品净化装置从生物样品中提取目标物质的方法。

公开(公告)号：US08361838B2

公开(公告)日：2013-01-29

申请号：US13241812

申请日：2011-09-23

Applicant: Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

Inventor： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

IPC: H01L21/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract translation: 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

公开(公告)号：US20120147516A1

公开(公告)日：2012-06-14

申请号：US13191890

申请日：2011-07-27

Applicant: Hyung Joon KIM ,  Jong Hoon Kim

Inventor： Hyung Joon KIM ,  Jong Hoon Kim

IPC: H01G4/30 ,  H01G4/12

CPC classification number: H01G4/1227 ,  H01G4/008 ,  H01G4/012 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30 ,  Y10T29/435

Abstract: Disclosed are a multilayer ceramic condenser and a method for manufacturing the same. There is provided a multilayer ceramic condenser including: a multilayer main body in which a plurality of dielectric layers including a first side, a second side, a third side, and a fourth side are stacked; a first cover layer and a second cover layer forming the plurality of dielectric layers; a first dielectric layer disposed between the first cover layer and the second cover layer and printed with a first inner electrode pattern drawn to the first side; a second dielectric layer alternately stacked with the first dielectric layer and printed with a second inner electrode pattern drawn to the third side; and a first side portion and a second side portion each formed on the second side and the fourth side opposite to each other.

Abstract translation: 公开了一种多层陶瓷电容器及其制造方法。 提供了一种多层陶瓷电容器，包括：多层主体，其中堆叠包括第一侧，第二侧，第三侧和第四侧的多个电介质层; 形成所述多个电介质层的第一覆盖层和第二覆盖层; 第一电介质层，设置在第一覆盖层和第二覆盖层之间，并印刷有第一内部电极图案，其被绘制到第一侧; 第二电介质层，与所述第一电介质层交替堆叠并且印刷有第二内部电极图案，所述第二内部电极图案被绘制到所述第三侧; 以及分别形成在彼此相对的第二侧和第四侧上的第一侧部和第二侧部。

公开(公告)号：US20120135394A1

公开(公告)日：2012-05-31

申请号：US13255646

申请日：2010-03-11

Applicant: Yu-Jeong Kim ,  Wan-Lim Koo ,  Jong-Hoon Kim ,  Dae-Jin Jang ,  Jin-Cheol Seo ,  Seong-Youl Kim ,  Hae-Joon Park ,  Han Oh Park

Inventor： Yu-Jeong Kim ,  Wan-Lim Koo ,  Jong-Hoon Kim ,  Dae-Jin Jang ,  Jin-Cheol Seo ,  Seong-Youl Kim ,  Hae-Joon Park ,  Han Oh Park

IPC: C12Q1/70 ,  G01N21/64 ,  C12M1/40

CPC classification number: B03C1/01 ,  B03C1/288 ,  B03C1/30 ,  C12Q1/6844 ,  G01N35/0098 ,  Y02A90/26 ,  C12Q2561/113 ,  C12Q2537/143

Abstract: Provided are an apparatus for integrated real-time nucleic acid analysis and a method for detecting target a nucleic acid using the same, and more particularly an integrated real-time nucleic acid analysis for simultaneously performing qualitative analysis or quantitative analysis on genes from various kinds of plural biological samples and a method for detecting target a nucleic acid using the same. The apparatus for integrated real-time nucleic acid analysis and the method for detecting target a nucleic acid using the same according to the present invention, perform tests of various targets required from various samples through a single step promptly and accurately, and thus, can be efficiently used by hospitals or the like needing to rapidly diagnose diseases.

Abstract translation: 提供了一种用于综合实时核酸分析的装置和使用其的核酸检测靶的方法，更具体地，涉及用于同时进行来自各种类型的基因的基因的定性分析或定量分析的综合实时核酸分析 多个生物样品和使用其的核酸检测靶标的方法。 用于综合实时核酸分析的装置和根据本发明的用于检测靶核酸的方法，通过一步一步地准确地进行各种样品所需的各种靶标的测试，因此可以 需要快速诊断疾病的医院等有效使用。

公开(公告)号：US08154135B2

公开(公告)日：2012-04-10

申请号：US12491651

申请日：2009-06-25

Applicant: Jong Hoon Kim ,  Ho Young Son

Inventor： Jong Hoon Kim ,  Ho Young Son

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L24/92 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/83194 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A stacked semiconductor package is presented which includes multiple semiconductor chips and through-electrodes. Each semiconductor chip has bonding pads formed on a first surface of the semiconductor chip and has a projection which projects from a portion of a second surface of the semiconductor chip. The first and second surfaces of the semiconductor chip face away from each other the first surface. The through-electrodes pass through the first surface and through the projection on the second surface.

Abstract translation: 提出了一种堆叠的半导体封装，其包括多个半导体芯片和通孔。 每个半导体芯片具有形成在半导体芯片的第一表面上的接合焊盘，并且具有从半导体芯片的第二表面的一部分突出的突起。 半导体芯片的第一和第二表面相对于第一表面。 贯通电极穿过第一表面并穿过第二表面上的突起。

公开(公告)号：US08116093B2

公开(公告)日：2012-02-14

申请号：US12132309

申请日：2008-06-03

Applicant: Kwang-Soo Park ,  Jong-Hoon Kim

Inventor： Kwang-Soo Park ,  Jong-Hoon Kim

IPC: H05K7/12 ,  H05K1/11

CPC classification number: H05K1/114 ,  H05K2201/094 ,  H05K2201/10734

Abstract: A printed circuit board (PCB) includes a substrate having a first group of at least two via holes and a second group of at least two via holes formed therein, a first pad set of terminal pads and a second pad set of terminal pads formed on the substrate, and a first group of conductive connection members and a second group of conductive connection members formed in the substrate. The first group of the via holes are surrounded by the first pad set of the terminal pads and the second group of the via holes are surrounded by the second pad set of the terminal pads. The first and the second groups of conductive connection members fill up the first and second groups of the via holes. The first group of the conductive connection members are connected to the first pad set of the terminal pads and the second group of the conductive connection members are connected to the second pad set of the terminal pads.

Abstract translation: 印刷电路板（PCB）包括：具有至少两个通孔的第一组的基板和形成在其中的至少两个通孔的第二组，第一焊盘组的端子焊盘和形成在 所述基板以及形成在所述基板中的第一组导电连接构件和第二组导电连接构件。 第一组通孔由端子焊盘的第一焊盘组围绕，并且第二组通孔被端子焊盘的第二焊盘组包围。 第一和第二组导电连接构件填充第一组和第二组通孔。 第一组导电连接构件连接到端子焊盘的第一焊盘组，并且第二组导电连接构件连接到端子焊盘的第二焊盘组。

公开(公告)号：US08110910B2

公开(公告)日：2012-02-07

申请号：US12731346

申请日：2010-03-25

Applicant: Jong Hoon Kim

Inventor： Jong Hoon Kim

IPC: H01L23/02

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/05599

Abstract: A stack package includes a first semiconductor chip possessing a first size and one or more second semiconductor chips possessing a second size greater than the first size. The first semiconductor chip has a first surface on which bonding pads are disposed, a second surface which faces away from the first surface, and first through-electrodes which pass through the first surface and the second surface. The one or more second semiconductor chips are stacked on the second surface of the first semiconductor chip and have second through-electrodes which are electrically connected to the first through-electrodes. A molding part abuts one or more side surfaces of the first semiconductor chip such that a total size including the first size and a size of the molding part is equal to or greater than the second size.

Abstract translation: 堆叠封装包括具有第一尺寸的第一半导体芯片和具有大于第一尺寸的第二尺寸的一个或多个第二半导体芯片。 第一半导体芯片具有设置接合焊盘的第一表面，远离第一表面的第二表面和穿过第一表面和第二表面的第一通孔。 一个或多个第二半导体芯片堆叠在第一半导体芯片的第二表面上，并且具有电连接到第一贯通电极的第二贯穿电极。 模制部件邻接第一半导体芯片的一个或多个侧表面，使得包括第一尺寸和成型部件的尺寸的总尺寸等于或大于第二尺寸。