公开(公告)号：US09570583B2

公开(公告)日：2017-02-14

申请号：US15255628

申请日：2016-09-02

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/283 ,  H01L21/3083 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract translation: 本发明的实施例可以包括将嵌入的蚀刻阻挡层结合到具有替换金属栅极的场效应晶体管（FET）的替换金属栅极层以及由此形成的结构的方法。 嵌入的蚀刻停止层可以由嵌入的掺杂剂原子组成，并且可以使用离子注入形成。 嵌入的蚀刻停止层可以使得替换金属栅极层的移除更容易和更可控，从而提供水平表面和确定的深度以用作栅极盖形成的基底。 栅极帽可以将栅极与相邻的自对准电触头绝缘。

公开(公告)号：US09553032B2

公开(公告)日：2017-01-24

申请号：US15092233

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/265 ,  H01L21/266 ,  H01L29/32

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

Abstract translation: 通过控制半导体鳍片的表面上沉积的半导体材料的生长速率，可以在同一衬底上同时形成半导体鳍片上的合并和未熔合的凸起的有源区域。 在一个实施例中，生长速率缓冲掺杂剂可以通过成角度的离子注入注入第一半导体鳍片的侧壁表面上，在第二半导体鳍片被掩模层掩蔽的同时，其中需要延长生长速率。 在另一个实施例中，通过离子注入可以将生长速率增强掺杂剂注入到第二半导体鳍片的侧壁表面上，而第一半导体鳍片被掩蔽层掩蔽。 沉积的半导体材料的不同的生长速率可以使得第一半导体散热片上的凸起的有源区域保持不熔化，并且使第二半导体鳍片上的有源区域升高以合并。

公开(公告)号：US09548356B2

公开(公告)日：2017-01-17

申请号：US14714779

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kerber ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US20160276275A1

公开(公告)日：2016-09-22

申请号：US15167306

申请日：2016-05-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material.

Abstract translation: MIS接触结构包括半导体材料层，具有形成在其中的接触开口的绝缘材料层，具有基本上垂直取向的部分和基本上水平取向的部分的接触绝缘材料层，接触层的垂直取向部分 绝缘材料接触接触开口的侧壁的部分而不是全部接触半导体层的接触绝缘材料层的水平取向部分。 导电材料位于接触开口内的接触绝缘材料层上，导电材料层具有垂直取向的部分和水平取向的部分，以及定位在接触开口中的导电触点，其接触导电材料层的最上表面， 接触层绝缘材料。

公开(公告)号：US20160254195A1

公开(公告)日：2016-09-01

申请号：US14633353

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/161 ,  H01L29/16 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract translation: 本文公开的一种说明性方法包括形成多个初始翅片，其具有与基底相同的初始轴向长度和相同的初始应变，执行至少一个蚀刻工艺以将第一翅片切割成第一轴向 并且将第二翅片切割成小于第一轴向长度的第二轴向长度，其中切割的第一翅片保持初始应变的第一量，并且切割的第二翅片保持初始应变的约零或第二量 的初始应变小于第一量，并且围绕第一和第二切割翅片形成栅极结构以形成FinFET器件。

公开(公告)号：US09412740B2

公开(公告)日：2016-08-09

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US20160225677A1

公开(公告)日：2016-08-04

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/84 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域

公开(公告)号：US09401373B2

公开(公告)日：2016-07-26

申请号：US14641462

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate.

公开(公告)号：US09378972B2

公开(公告)日：2016-06-28

申请号：US14632313

申请日：2015-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Matthew E. Colburn ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/311 ,  H01L21/308 ,  H01L27/088 ,  H01L21/84 ,  H01L27/108 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L21/3086 ,  H01L21/3088 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/1104 ,  H01L29/0657

Abstract: Methods for forming semiconductor devices. Methods for forming fin structures include forming first sidewalls around a first set of mandrels. The first set of mandrels is removed and second sidewalls are formed around the first sidewalls and a second set of mandrels. The first sidewalls and the second set of mandrels are removed and an underlying layer around the second sidewalls is etched.

Abstract translation: 半导体器件形成方法。 形成翅片结构的方法包括围绕第一组心轴形成第一侧壁。 去除第一组心轴，并且在第一侧壁和第二组心轴周围形成第二侧壁。 去除第一侧壁和第二组心轴，并且蚀刻围绕第二侧壁的下层。

公开(公告)号：US09373691B2

公开(公告)日：2016-06-21

申请号：US13961282

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L21/04 ,  H01L29/78 ,  H01L29/16 ,  H01L21/762

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/76254 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate.

Abstract translation: 一种形成半导体器件的方法包括在第一衬底上形成电介质层，并将第一衬底的电介质层与包含SiC的第二衬底相结合，并在SiC上形成钝化层。 从与电介质层相对的一侧去除第一衬底的一部分。 对电介质层进行构图以形成用于形成在第二衬底上的场效应晶体管的栅极电介质。