公开(公告)号：US11408720B2

公开(公告)日：2022-08-09

申请号：US17209738

申请日：2021-03-23

申请人： Unimicron Technology Corporation

发明人： Cheng-Jui Chang ,  Hung-Lin Chang ,  Jeng-Wey Chiang

IPC分类号： G01B7/06 ,  G01R1/067 ,  G01B7/00

摘要： A method for measuring thickness of dielectric layer in circuit board includes the following steps: First, circuit board including dielectric layer and circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes test area including test pattern and through hole. The test pattern includes first conductor and second conductors. The distance between the side of the through hole and the second conductor is less than the distance between the side of the through hole and the first conductor. Next, measuring device including conductive pin and sensing element is provided. Next, the conductive pin is powered, and one end of the conductive pin is electrically connected to the second conductor. Next, the sensing element is moved along the through hole to obtain sensing curve, and the thickness of the dielectric layer is calculated via variations of the sensing curve.

公开(公告)号：US20210378092A1

公开(公告)日：2021-12-02

申请号：US16944178

申请日：2020-07-31

申请人： UNIMICRON TECHNOLOGY CORPORATION

发明人： YI LIN ,  HSIAO-HAN HUANG ,  YU-HSIN PAN

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/10 ,  H05K3/40

摘要： Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.

公开(公告)号：US10820411B1

公开(公告)日：2020-10-27

申请号：US16879951

申请日：2020-05-21

申请人： Unimicron Technology Corporation

发明人： Shih-Lian Cheng ,  Zhe-Yong Lin ,  Li-Jie Liu ,  Ching Sheng Chen

IPC分类号： H05K1/02 ,  H05K3/02 ,  H05K1/09 ,  H05K3/06

摘要： A manufacturing method for a circuit board and a circuit board are provided. The method includes steps: providing a substrate having a first metal layer; forming a patterned first opening on the first metal layer to expose the substrate; forming a patterned first dielectric layer on the substrate, the first dielectric layer is made of a photosensitive dielectric material and covers the first opening; photosensitizing the first dielectric layer to cure the first dielectric layer; forming a patterned second metal layer on the first metal layer; forming a patterned third metal layer on the second metal layer, and the third metal layer being adjacent to the first dielectric layer; removing a portion of the first metal layer not covered by the second metal layer; and forming a second dielectric layer on the substrate. A thickness of the third metal layer is greater than a thickness of the second metal layer.

公开(公告)号：US09385056B2

公开(公告)日：2016-07-05

申请号：US13566323

申请日：2012-08-03

申请人： Dyi-Chung Hu ,  John Hon-Shing Lau

发明人： Dyi-Chung Hu ,  John Hon-Shing Lau

IPC分类号： H01L23/14 ,  H01L23/498 ,  H01L23/13

CPC分类号： H01L23/147 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  Y10T29/49165 ,  H01L2224/05599

摘要： A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

摘要翻译： 封装基板包括载体和插入件。 载体具有相对的顶部和底部表面。 在顶面形成有凹部，在凹部上形成有多个第一导电端子。 此外，在载体的底表面上形成多个第二导电端子。 插入器设置在凹部中并且具有相对的第一和第二表面以及穿过第一表面和第二表面的多个导电通孔。 第一导电焊盘形成在从第一表面暴露的每个导电通孔的端部上，并且第二导电焊盘形成在从第二表面暴露的每个导电通孔的另一端上并且电连接到 对应的第一导电端子之一。 与现有技术相比，本发明提高了产品的可靠性。

公开(公告)号：US09230899B2

公开(公告)日：2016-01-05

申请号：US13406673

申请日：2012-02-28

申请人： Wen-Lung Lai ,  Yuan-Liang Lo

发明人： Wen-Lung Lai ,  Yuan-Liang Lo

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H05K3/00 ,  H05K3/20 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/205 ,  Y10T29/49165 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

摘要： A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided.

摘要翻译： 封装基板包括保持器，设置在保持器上的第一导电焊盘，设置在保持器上的芯层，设置在芯层上的电路层，设置在芯层中的多个导电通孔，以及设置在绝缘保护层 在所述芯层上，其中所述第一电垫嵌入所述芯层中。 通过在包装基板的一侧上组合保持件，可以防止在转印或包装过程中由于过度的破裂。 还提供了制造封装衬底的方法，具有保持器的封装结构，制造封装结构的方法。

公开(公告)号：US09111818B2

公开(公告)日：2015-08-18

申请号：US14018757

申请日：2013-09-05

申请人： Unimicron Technology Corporation

发明人： Chun-Ting Lin ,  Yu-Chung Hsieh ,  Ying-Tung Wang ,  Ying-Chih Chan

IPC分类号： H05K7/10 ,  H05K7/12 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/40

CPC分类号： H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11422 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/4007 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A packaging substrate is provided, including a substrate body having a plurality of conductive pads, an insulating protective layer formed on the substrate body for the conductive pads to be exposed therefrom, and a plurality of conductive pillars disposed on the conductive pads. Each of the conductive pillars has a bottom end and a top end narrower than the bottom end, thereby forming a cone-shaped structure that does not have a wing structure. Therefore, the distance between contact points is reduced and the demands for fine-pitch and multi-joints are satisfied.

摘要翻译： 提供一种封装基板，包括具有多个导电焊盘的基板主体，形成在基板主体上用于要暴露的导电焊盘的绝缘保护层，以及设置在导电焊盘上的多个导电柱。 每个导电柱具有比底端窄的底端和顶端，从而形成不具有翼结构的锥形结构。 因此，接触点之间的距离减小，满足细间距和多关节的要求。

公开(公告)号：US09070616B2

公开(公告)日：2015-06-30

申请号：US14097656

申请日：2013-12-05

申请人： Unimicron Technology Corporation

发明人： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/19 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029

摘要： A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.

摘要翻译： 封装基板包括第一介电层; 多个第一导电焊盘，其嵌入并暴露于所述第一介电层的第一表面; 第一电路层，其被嵌入并暴露于所述第一介电层的第二表面; 设置在第一电介质层中的多个第一金属凸块，每个第一金属凸块具有嵌入在第一电路层中的第一端和与第一端相对的第二端并且设置在第一导电焊盘之一上，导电种子层 设置在第一电路层和第一电介质层之间以及第一电路层和第一金属凸块之间; 布置在第一电路层和第一介电层上的叠层结构; 以及设置在所述积层结构上的多个第二导电焊盘。 包装衬底具有改善的超翘曲问题。

公开(公告)号：US08884429B2

公开(公告)日：2014-11-11

申请号：US13352664

申请日：2012-01-18

申请人： Zhao-Chong Zeng

发明人： Zhao-Chong Zeng

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/14 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

摘要： A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

摘要翻译： 具有嵌入式电子部件的封装结构包括：具有穿透其中的空腔的载体; 半导体芯片，其容纳在所述空腔中，并且在其上设置有焊料凸块 形成在所述载体和所述半导体芯片上以封装所述焊料凸块的电介质层; 形成在电介质层上的布线层; 形成在所述电介质层和所述布线层上的绝缘保护层; 以及形成在电介质层中的焊料材料和用于电连接布线层和焊料凸块的绝缘保护层，从而缩短半导体芯片和载体之间的信号传输路径，以避免信号损失。

公开(公告)号：US20140264335A1

公开(公告)日：2014-09-18

申请号：US13845800

申请日：2013-03-18

申请人： UNIMICRON TECHNOLOGY CORPORATION

发明人： Dyi-Chung Hu ,  Tsung-Si Wang ,  Jui-Yang Ma

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  H01L22/32 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads disposed in the testing region and electrically connected to the conductive pads, wherein the top surface area of each of the testing pads is greater than the top surface area of each of the conductive pads in order to facilitate a precise alignment of a probe with a corresponding one of the testing pads and prevent the probe from being blocked by the board body when in electrically testing an embedded circuit.

摘要翻译： 提供一种封装基板，包括具有布线区域和限定在其上的测试区域的板体，嵌入布线区域中的导电焊盘以及设置在测试区域中并电连接到导电焊盘的多个测试焊盘，其中， 每个测试焊盘的顶表面积大于每个导电焊盘的顶表面积，以便于探针与对应的一个测试焊盘的精确对准，并防止探针被板阻挡 身体在电测试嵌入式电路时。

公开(公告)号：US20140263168A1

公开(公告)日：2014-09-18

申请号：US14088782

申请日：2013-11-25

申请人： Unimicron Technology Corporation

发明人： Shih-Lian Cheng ,  Jui-Jung Chien

IPC分类号： H05K3/00 ,  H05K3/10

CPC分类号： H05K3/0017 ,  H01L21/486 ,  H05K3/107 ,  H05K2201/0376 ,  H05K2201/09036

摘要： A method for manufacturing a package substrate is provided, including etching a substrate to form trenches each having a buffer portion, and forming a circuit in each of the trenches. The trenches are formed by etching instead of excimer laser to increase the aspect ratio of the trench, thereby solving the problem that the metallic layer is not thick enough and achieving a high yield of the circuit and a good process capability index.

摘要翻译： 提供了一种制造封装衬底的方法，包括蚀刻衬底以形成各自具有缓冲部分的沟槽，并且在每个沟槽中形成电路。 通过蚀刻而不是准分子激光形成沟槽，以增加沟槽的纵横比，从而解决了金属层不够厚并且实现电路的高产率和良好的工艺能力指数的问题。