公开(公告)号：US08665591B2

公开(公告)日：2014-03-04

申请号：US12974512

申请日：2010-12-21

Applicant: Richard Bourgeois ,  Kristopher Frutschy ,  Mohamed Sakami ,  William Waters ,  Mao Leng

Inventor： Richard Bourgeois ,  Kristopher Frutschy ,  Mohamed Sakami ,  William Waters ,  Mao Leng

IPC: H05K7/20

CPC classification number: H01M10/399 ,  H01M10/425 ,  H01M10/486 ,  H01M10/617 ,  H01M10/6563 ,  H01M10/6568

Abstract: A system for an electronic device includes a housing having one or more walls that define an internal region. An outlet port is fluidically coupled to the internal region of the housing, which allows emission of a fluid from the internal region of the housing as a first flow at a first temperature. A merging element, fluidically coupled to the outlet port, merges the first flow with a second flow, which has a second temperature that is less than the first temperature.

Abstract translation: 一种用于电子设备的系统包括具有限定内部区域的一个或多个壁的壳体。 出口端口流体耦合到壳体的内部区域，这允许从壳体的内部区域排出流体作为第一温度的第一流量。 流体耦合到出口的合并元件将第一流与第二流合并，第二流具有小于第一温度的第二温度。

公开(公告)号：US20120155025A1

公开(公告)日：2012-06-21

申请号：US12974512

申请日：2010-12-21

Applicant: Richard Bourgeois ,  Kristopher Frutschy ,  Mohamed Sakami ,  William Waters ,  Mao Leng

Inventor： Richard Bourgeois ,  Kristopher Frutschy ,  Mohamed Sakami ,  William Waters ,  Mao Leng

IPC: H05K7/20

CPC classification number: H01M10/399 ,  H01M10/425 ,  H01M10/486 ,  H01M10/617 ,  H01M10/6563 ,  H01M10/6568

Abstract: A system for an electronic device includes a housing having one or more walls that define an internal region. An outlet port is fluidically coupled to the internal region of the housing, which allows emission of a fluid from the internal region of the housing as a first flow at a first temperature. A merging element, fluidically coupled to the outlet port, merges the first flow with a second flow, which has a second temperature that is less than the first temperature.

Abstract translation: 一种用于电子设备的系统包括具有限定内部区域的一个或多个壁的壳体。 出口端口流体耦合到壳体的内部区域，这允许从壳体的内部区域排出流体作为第一温度的第一流量。 流体耦合到出口的合并元件将第一流与第二流合并，第二流具有小于第一温度的第二温度。

公开(公告)号：US20060060979A1

公开(公告)日：2006-03-23

申请号：US10947515

申请日：2004-09-22

Applicant: Kristopher Frutschy

Inventor： Kristopher Frutschy

IPC: H01L23/52

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/10 ,  H01L24/13 ,  H01L24/97 ,  H01L2224/0554 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/7598 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81224 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods and systems for attaching a chip to a next level package by directing radiant energy at the chip back side while substantially preventing irradiation of the next level package are described.

Abstract translation: 描述了通过在芯片背面引导辐射能而基本上防止下一级封装的照射来将芯片附接到下一级封装的方法和系统。

公开(公告)号：US20120129022A1

公开(公告)日：2012-05-24

申请号：US13189867

申请日：2011-07-25

Applicant: Peter KALISH ,  Kashyap Shah ,  Kristopher Frutschy ,  Stuart Towie ,  James Browell ,  Roger Bull ,  Ajith Kuttannair Kumar ,  Michael Patrick Marley ,  John D. Butine ,  Harold Alan Ellsworth ,  John L. Donner ,  Stephen Pelkowski ,  Owen Scott Quirion ,  Neil A. Johnson

Inventor： Peter KALISH ,  Kashyap Shah ,  Kristopher Frutschy ,  Stuart Towie ,  James Browell ,  Roger Bull ,  Ajith Kuttannair Kumar ,  Michael Patrick Marley ,  John D. Butine ,  Harold Alan Ellsworth ,  John L. Donner ,  Stephen Pelkowski ,  Owen Scott Quirion ,  Neil A. Johnson

IPC: H01M2/10 ,  H01M10/04 ,  H01M10/50 ,  H01M2/30 ,  H01M10/48

CPC classification number: H01M2/1077 ,  H01M2/1088 ,  H01M2/206 ,  H01M2/208 ,  H01M10/39 ,  H01M10/613 ,  H01M10/625 ,  H01M10/647 ,  H01M10/6556 ,  H01M10/6557 ,  H01M10/6567 ,  H01M10/658 ,  Y10T29/49117

Abstract: An electrochemical device is disclosed that includes a plurality of cells that each include a face, wherein a terminal is disposed on the faces of each respective cell. A bus bar has a bus bar height and electrically couples the terminals from cell-to-cell within the electrochemical device. A plurality of sheets are disposed between the plurality of cells, the plurality of sheets are substantially the same height as the combined, height of each cell and bus bar.

Abstract translation: 公开了一种电化学装置，其包括多个单元，每个单元包括面，其中端子设置在每个相应单元的表面上。 母线具有母线高度，并将端子与电化学装置内的电池电连接。 多个片材被设置在多个单元之间，多个片材与每个单元和母线的组合高度基本相同。

公开(公告)号：US20060044101A1

公开(公告)日：2006-03-02

申请号：US10932396

申请日：2004-09-01

Applicant: Kristopher Frutschy ,  Udbhava Shrivastava

Inventor： Kristopher Frutschy ,  Udbhava Shrivastava

IPC: H01F5/00

CPC classification number: H01L21/4857 ,  H01F17/0006 ,  H01F17/045 ,  H01F27/027 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/165 ,  H01L2224/0401

Abstract: Provided are methods and devices in which an inductor is embedded in a package adapted to carry an integrated circuit and a magnetically permeable material is also embedded in the package so that the inductor and the magnetically permeable material are magnetically coupled to each other. In one embodiment, the magnetic permeable material is shaped as a pin which is press-fit into the core of a helix-shaped inductor embedded in the package substrate.

Abstract translation: 提供了一种方法和装置，其中电感器嵌入在适于承载集成电路的封装中，并且导磁材料也嵌入封装中，使得电感器和导磁材料彼此磁耦合。 在一个实施例中，磁性可渗透材料成形为压入配合到嵌入在封装衬底中的螺旋形电感器的芯的引脚。

公开(公告)号：US20050280138A1

公开(公告)日：2005-12-22

申请号：US10873817

申请日：2004-06-21

Applicant: Udy Shrivastava ,  Kristopher Frutschy

Inventor： Udy Shrivastava ,  Kristopher Frutschy

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/4985 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package includes a first chip and a folded flexible substrate. The flexible substrate has a first surface and an opposing second surface and is disposed to partially surround the first chip. A first routing layer is formed on the first surface of the flexible substrate and a second routing layer is formed on the second surface of the flexible substrate. A metal ground plane is formed on a selected one of the first and the second surfaces.

Abstract translation: 集成电路封装包括第一芯片和折叠的柔性基板。 柔性基板具有第一表面和相对的第二表面，并且被设置成部分地围绕第一芯片。 第一布线层形成在柔性基板的第一表面上，第二布线层形成在柔性基板的第二表面上。 金属接地平面形成在所述第一和第二表面中的所选择的一个上。

公开(公告)号：US06639799B2

公开(公告)日：2003-10-28

申请号：US09746554

申请日：2000-12-22

Applicant: Ravi Prasher ,  Abhay A. Watwe ,  Gregory M. Chrysler ,  Kristopher Frutschy ,  Leo Ofman ,  Ajit V. Sathe

Inventor： Ravi Prasher ,  Abhay A. Watwe ,  Gregory M. Chrysler ,  Kristopher Frutschy ,  Leo Ofman ,  Ajit V. Sathe

IPC: H05K720

CPC classification number: H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Two types of thermal management devices for efficiently dissipating heat generated by high performance electronic devices, such as microprocessors for desktop and server computers producing a power of near 200 Watts and high power electronic devices that are small and thin, such as those used in telephones, radios, laptop computers, and handheld devices. An integrated heat sink and spreader for cooling an item has a vapor chamber heat sink with a thinner first wall and a thicker second wall. The thicker second wall is engageable with the item in efficient heat transferring relationship. A plurality of heat-radiating fins are attached to the thinner first wall. An embedded direct heat pipe attachment includes a heat pipe embedded in a spreader plate that is in direct heat transferring contact with an item through a thin, uniform layer of thermal interface material.

公开(公告)号：US20070231952A1

公开(公告)日：2007-10-04

申请号：US11395102

申请日：2006-03-31

Applicant: Kristopher Frutschy ,  Sudarshan Rangaraj ,  Kevin George

Inventor： Kristopher Frutschy ,  Sudarshan Rangaraj ,  Kevin George

IPC: H01L21/00

CPC classification number: H05K3/3494 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81054 ,  H01L2224/81209 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/3436 ,  H05K2203/1121 ,  H01L2924/00 ,  H01L2924/3512

Abstract: Method of forming a microelectronic package using control of die and substrate differential expansions. The method includes: providing a die-substrate combination including a substrate, a die disposed on the substrate, and plurality of solder paste disposed between the die and the substrate; reflowing the solder paste by exposing the die-substrate combination to temperatures changes including heating the die-substrate combination to liquefy the solder paste, and cooling down the die-substrate combination until the solder paste has solidified to form solder joints to yield the package; and controlling an expansion of the die and the substrate at least during cooling down to mitigate a relative difference in volumetric strain between the die and the substrate. Controlling may comprise exposing the die-substrate combination to pressure changes at least during cooling down.

Abstract translation: 使用管芯和衬底差分扩展的控制形成微电子封装的方法。 该方法包括：提供包括基板，设置在基板上的管芯和设置在管芯和基板之间的多个焊膏的管芯基板组合; 通过将模具 - 基板组合暴露于包括加热模具 - 基板组合以液化焊膏的温度变化，以及冷却模具 - 基板组合直到焊膏固化形成焊点以产生封装，来回流焊膏; 以及至少在冷却期间控制模具和基材的膨胀以减轻模头和基板之间的体积应变的相对差异。 控制可以包括至少在冷却期间使模具 - 基板组合暴露于压力变化。

公开(公告)号：US07154175B2

公开(公告)日：2006-12-26

申请号：US10873817

申请日：2004-06-21

Applicant: Udy A. Shrivastava ,  Kristopher Frutschy

Inventor： Udy A. Shrivastava ,  Kristopher Frutschy

IPC: H01L23/34

CPC classification number: H01L23/4985 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package includes a first chip and a folded flexible substrate. The flexible substrate has a first surface and an opposing second surface and is disposed to partially surround the first chip. A first routing layer is formed on the first surface of the flexible substrate and a second routing layer is formed on the second surface of the flexible substrate. A metal ground plane is formed on a selected one of the first and the second surfaces.

Abstract translation: 集成电路封装包括第一芯片和折叠的柔性基板。 柔性基板具有第一表面和相对的第二表面，并且被设置成部分地围绕第一芯片。 第一布线层形成在柔性基板的第一表面上，第二布线层形成在柔性基板的第二表面上。 金属接地平面形成在所述第一和第二表面中的所选择的一个上。

公开(公告)号：US06428358B1

公开(公告)日：2002-08-06

申请号：US09750419

申请日：2000-12-28

Applicant: David G. Figueroa ,  Chee-Yee Chung ,  Kristopher Frutschy ,  Farzaneh Yahyaei-Moayyed

Inventor： David G. Figueroa ,  Chee-Yee Chung ,  Kristopher Frutschy ,  Farzaneh Yahyaei-Moayyed

IPC: H01R13648

CPC classification number: H01R13/6585 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49211 ,  Y10T29/49222

Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber. Accordingly, the walls of the conductive structure function as a ground plane that surrounds the signal carrying and power conducting contacts.

Abstract translation: 插座（300，图3）包括具有形成在顶表面中的多个开口（304）的壳体（302）。 每个开口（304）提供对导电触点（502，图5）的访问，其提供插入到插座中的装置与下一级互连（例如，PC板）之间的电接口。 嵌入在插座内的是导电结构（图3中的310）。 在一个实施例中，导电结构电连接到一个或多个接地导电触头（图7的708）。 导电结构包括与触点列平行延伸的柱壁（312）和平行于触点行并与柱壁相交的行壁（314）。 以这种方式，导电结构形成多个室（图4中的402）。 每个信号承载和电力传导触点位于一个室内。 因此，导电结构的壁用作围绕信号承载和电力传导触点的接地平面。