公开(公告)号：US09761506B2

公开(公告)日：2017-09-12

申请号：US13403341

申请日：2012-02-23

申请人： Takukazu Otsuka ,  Bryon Western ,  Brandon Passmore ,  Zach Cole

发明人： Takukazu Otsuka ,  Bryon Western ,  Brandon Passmore ,  Zach Cole

IPC分类号： H01L23/34 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00

CPC分类号： H01L23/3735 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/8182 ,  H01L2224/8383 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/00

摘要： Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor device 1 comprising: a mounting substrate 70; a semiconductor chip 10 disposed on the mounting substrate 70 and a semiconductor substrate 26, a source pad electrode SP and a gate pad electrode GP disposed on a surface of the semiconductor substrate 26, and a drain pad electrode 36 disposed on a back side surface of the semiconductor substrate 26 to be contacted with the mounting substrate 70; and a source connector SC disposed on the source pad electrode SP. The mounting substrate 70 and the drain pad electrode 36 are bonded by using solid phase diffusion bonding.

公开(公告)号：US08971044B2

公开(公告)日：2015-03-03

申请号：US13479032

申请日：2012-05-23

申请人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

发明人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

IPC分类号： H05K7/20 ,  H01L25/18 ,  H01L25/16 ,  H02M7/00 ,  H05K1/14

CPC分类号： H02M7/003 ,  H01L25/162 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H05K1/14 ,  H05K7/02 ,  H05K7/20509 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.

摘要翻译： 半导体器件包括：第一输出单元，被配置为输出第一相位; 第二输出单元，被配置为输出与所述第一相不同的第二相，所述第二输出单元被布置为堆叠在所述第一输出单元上; 以及控制器，被配置为控制所述输出单元。

公开(公告)号：US20120112201A1

公开(公告)日：2012-05-10

申请号：US12942437

申请日：2010-11-09

申请人： Takukazu OTSUKA ,  Keiji OKUMURA ,  Brian LYNN ROWDEN

发明人： Takukazu OTSUKA ,  Keiji OKUMURA ,  Brian LYNN ROWDEN

IPC分类号： H01L23/498 ,  B32B15/01 ,  B23K1/20 ,  H01L29/02 ,  H01L23/492

CPC分类号： B32B15/018 ,  B23K1/0016 ,  B23K35/0238 ,  B23K35/262 ,  B23K35/3006 ,  B23K2101/40 ,  H01L23/053 ,  H01L23/3735 ,  H01L23/488 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/271 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29155 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83204 ,  H01L2224/83211 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3841 ,  Y10T428/12708 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high melting point soldering layer includes a low melting point metal layer, a first high melting point metal layer disposed on a surface of the low melting point metal layer, and a second high melting point metal layer disposed at a back side of the low melting point metal layer. The low melting point metal layer, the first high melting point metal layer, and the second high melting point metal layer are mutually alloyed by transient liquid phase bonding, by annealing not less than a melting temperature of the low melting point metal layer, diffusing the metal of the low melting point metal layer into an alloy of the first high melting point metal layer and the second high melting point metal layer. The high melting point soldering layer has a higher melting point temperature than that of the low melting point metal layer. It is provided a binary based high melting point soldering layer having TLP bonding of a high melting point according to a low temperature processing, a fabrication method for the high melting point soldering layer and a semiconductor device to which the high melting point soldering layer is applied.

摘要翻译： 高熔点焊接层包括低熔点金属层，设置在低熔点金属层的表面上的第一高熔点金属层和设置在低熔点金属层的背面的第二高熔点金属层 点金属层。 低熔点金属层，第一高熔点金属层和第二高熔点金属层通过瞬态液相结合相互合金化，通过退火不低于低熔点金属层的熔融温度，将 低熔点金属层的金属成为第一高熔点金属层和第二高熔点金属层的合金。 高熔点焊接层的熔点温度高于低熔点金属层。 提供了一种基于低温处理的具有高熔点TLP键合的二元基高熔点焊接层，用于高熔点焊接层的制造方法和施加高熔点焊接层的半导体器件 。

公开(公告)号：US20130092948A1

公开(公告)日：2013-04-18

申请号：US13275423

申请日：2011-10-18

申请人： Takukazu OTSUKA

发明人： Takukazu OTSUKA

IPC分类号： H01L29/20 ,  B23K20/00 ,  B23K31/02 ,  H01L23/48

CPC分类号： H01L24/29 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7802 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29023 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81091 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/8183 ,  H01L2224/83091 ,  H01L2224/83097 ,  H01L2224/8383 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01014 ,  H01L2924/01006 ,  H01L2924/00

摘要： The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding.

摘要翻译： 具有倒装芯片结构的半导体器件包括：绝缘基板; 设置在所述绝缘基板上的信号布线电极; 电力布线电极，设置在所述绝缘基板上，或者配置成穿过所述绝缘基板; 半导体芯片，其以倒装芯片配置设置在所述绝缘基板上，并且包括半导体衬底，设置在所述半导体衬底的表面上的源极焊盘电极和栅极焊盘电极，以及设置在所述半导体衬底的背侧表面上的漏极焊盘电极 基质; 设置在栅极焊盘电极上的玛瑙连接器; 以及设置在源极焊盘电极上的源极连接器。 通过使用固相扩散接合，键合栅极连接器，栅极焊盘电极和信号布线电极，并且源极连接器，源极焊盘电极和电力布线电极接合。

公开(公告)号：US07864533B2

公开(公告)日：2011-01-04

申请号：US12826334

申请日：2010-06-29

申请人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

发明人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

IPC分类号： H05K7/20

CPC分类号： H02M7/003 ,  H01L25/162 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H05K1/14 ,  H05K7/02 ,  H05K7/20509 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.

摘要翻译： 半导体器件包括：第一输出单元，被配置为输出第一相位; 第二输出单元，被配置为输出与所述第一相不同的第二相，所述第二输出单元被布置为堆叠在所述第一输出单元上; 以及控制器，被配置为控制所述输出单元。

公开(公告)号：US20090166893A1

公开(公告)日：2009-07-02

申请号：US12342161

申请日：2008-12-23

申请人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

发明人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

IPC分类号： H01L23/49

CPC分类号： H01L24/33 ,  H01L23/49811 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/27505 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: an insulating substrate; a metal bonding member being disposed on the insulating substrate and having a porous region and a metal region, the porous region being provided with multiple pores therein and being adjacent to the metal region in a plane direction of the insulating substrate; a solder material impregnated into the pores; a semiconductor element disposed on the surface of the porous region in the metal bonding member; a bonding wire connected to the surface of the metal region in the metal bonding member. This makes it possible to provide a semiconductor device having improved electrical conductivity and thermal conductivity, and enabling the weight reduction.

摘要翻译： 根据本发明的半导体器件包括：绝缘基板; 金属接合构件设置在绝缘基板上并具有多孔区域和金属区域，多孔区域在绝缘基板的平面方向上设置有多个孔并且与金属区域相邻; 浸入孔中的焊料; 设置在所述金属接合部件的所述多孔区域的表面上的半导体元件; 连接到金属接合部件中的金属区域的表面的接合线。 这使得可以提供具有改善的导电性和导热性并且能够实现重量减轻的半导体器件。

公开(公告)号：US08410600B2

公开(公告)日：2013-04-02

申请号：US12876614

申请日：2010-09-07

申请人： Alexander B. Lostetter ,  Jared Hornberger ,  Takukazu Otsuka

发明人： Alexander B. Lostetter ,  Jared Hornberger ,  Takukazu Otsuka

IPC分类号： H01L29/41

CPC分类号： H01L21/84 ,  H01L21/0485 ,  H01L21/6715 ,  H01L24/24 ,  H01L29/66068 ,  H01L2224/24998 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.

摘要翻译： 提供半导体器件和制造半导体器件的方法，该半导体器件包括：源极迹线，漏极迹线和置于衬底上的栅极迹线; 放置在漏极迹线上并包括源极焊盘和栅极焊盘的晶体管; 绝缘膜放置在漏极和源极之间以及衬底上的漏极和栅极迹线之间，以覆盖晶体管的侧壁表面; 源极喷射电极，放置在源极和漏极迹线之间的绝缘膜上，并连接晶体管的源极焊盘和源极迹线; 以及栅极喷射电极，其放置在栅极和漏极迹线之间的绝缘膜上，并连接晶体管的栅极焊盘和栅极迹线。

公开(公告)号：US20110012132A1

公开(公告)日：2011-01-20

申请号：US12866528

申请日：2009-02-06

申请人： Takukazu Otsuka ,  Shuhei Mitani

发明人： Takukazu Otsuka ,  Shuhei Mitani

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： Provided is a semiconductor device which has improved withstand voltage and can be manufactured by simpler manufacturing process. The semiconductor device according to the present invention includes: a SiC-containing n-type epitaxial layer 1 which is stacked on a surface of the n+-type substrate 11 containing SiC; n+-type source regions 5 arranged away from each other in a surface layer of the epitaxial layer 1; a p-type well contact region 2 sandwiched by the source regions 5; a p-type well region 3 arranged in contact with surfaces of the source regions 5 and p-type well contact region 2 on the substrate 11 side; and p-type well extension regions 4 arranged to sandwich the source regions 5 and p-type well region 3. The impurity concentration of the p-type well region 3 has a peak concentration at a position deeper in the depth direction from the surface of the epitaxial layer 1 toward the substrate 11 than the position of a peak concentration of the p-type well extension regions 4.

摘要翻译： 提供了具有改善的耐受电压并且可以通过更简单的制造工艺制造的半导体器件。 根据本发明的半导体器件包括：层叠在包含SiC的n +型衬底11的表面上的含SiC的n型外延层1; 在外延层1的表面层中彼此远离配置的n +型源极区域5; 由源极区域5夹持的p型阱接触区域2; 与基板11侧的源极区域5和p型阱接触区域2的表面配置的p型阱区域3。 以及p型阱延伸区域4，其被布置成夹持源极区域5和p型阱区域3. p型阱区域3的杂质浓度在距离表面的深度方向上更深的位置具有峰值浓度 外延层1相对于p型阱延伸区域4的峰值浓度的位置朝向衬底11。

公开(公告)号：US07773381B2

公开(公告)日：2010-08-10

申请号：US12234761

申请日：2008-09-22

申请人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

发明人： Keiji Okumura ,  Takukazu Otsuka ,  Masao Saito

IPC分类号： H05K7/20

CPC分类号： H02M7/003 ,  H01L25/162 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2924/01019 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H05K1/14 ,  H05K7/02 ,  H05K7/20509 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.

摘要翻译： 半导体器件包括：第一输出单元，被配置为输出第一相位; 第二输出单元，被配置为输出与所述第一相不同的第二相，所述第二输出单元被布置为堆叠在所述第一输出单元上; 以及控制器，被配置为控制所述输出单元。

公开(公告)号：US20090091892A1

公开(公告)日：2009-04-09

申请号：US12234771

申请日：2008-09-22

申请人： Takukazu Otsuka ,  Keiji Okumura ,  Masao Saito

发明人： Takukazu Otsuka ,  Keiji Okumura ,  Masao Saito

IPC分类号： H05K7/20

CPC分类号： H05K7/20918 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02M7/003 ,  H05K7/1432 ,  H01L2924/00

摘要： A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed on a plane intersecting with a plane having the first output unit disposed thereon; and a controller configured to control the output units.

摘要翻译： 半导体器件包括：第一输出单元，被配置为输出第一相位; 第二输出单元，被配置为输出与所述第一相不同的第二相，所述第二输出单元设置在与其上设置有所述第一输出单元的平面相交的平面上; 以及控制器，被配置为控制所述输出单元。