公开(公告)号：US20130168851A1

公开(公告)日：2013-07-04

申请号：US13484289

申请日：2012-05-31

Applicant: Yu-Min Lin ,  Chau-Jie Zhan ,  Tao-Chih Chang

Inventor： Yu-Min Lin ,  Chau-Jie Zhan ,  Tao-Chih Chang

IPC: H01L23/498 ,  H01L21/28

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2224/1146

Abstract: A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Abstract translation: 凸块结构包括基板，焊盘，电极和突出电极。 衬垫设置在衬底上。 电极由第一金属材料形成并设置在焊盘上。 突起电极由第二金属材料形成并设置在电极上，其中突出电极的横截面面积小于电极的横截面面积。

公开(公告)号：US20120270392A1

公开(公告)日：2012-10-25

申请号：US13537054

申请日：2012-06-29

Applicant: Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

Inventor： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

IPC: H01L21/768

CPC classification number: C23C14/165 ,  C23C14/3492 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

Abstract: A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract translation: 提供了一种有源器件阵列衬底的制造方法。 有源器件阵列衬底具有至少一个图案化导电层。 图案化导电层包括铜层。 铜层的与铜层的法线平行的截面包括层叠在第一梯形上的第一梯形和第二梯形。 第一梯形的底角和第二梯形的底角是锐角，第一梯形的底角与第二梯形的底角之间的差为约5°至约30°。

公开(公告)号：US08280081B2

公开(公告)日：2012-10-02

申请号：US12344270

申请日：2008-12-25

Applicant: Yu-Min Lin ,  Chang-Ho Liou ,  Yu-Wei Huang ,  Ming-Daw Chen ,  Rong-Shen Lee

Inventor： Yu-Min Lin ,  Chang-Ho Liou ,  Yu-Wei Huang ,  Ming-Daw Chen ,  Rong-Shen Lee

IPC: H04R25/00

CPC classification number: H04R1/06

Abstract: An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area.

Abstract translation: 提供扬声器单元的电极连接结构。 扬声器单元包括至少一个电极层，该电极层由导电材料制成，或由其表面上形成有导电层的非导电材料制成。 电极连接结构包括导电电极和粘合材料。 导电电极用于为扬声器单元提供电源信号以产生声音。 粘合剂材料将导电电极与电极层的表面平行地粘合。 粘合剂材料具有粘合特性，以便以一定面积将导电电极和电极层电连接，其中粘合剂材料粘附到与导电电极紧密相邻的电极层的表面的一侧。

公开(公告)号：US08107817B2

公开(公告)日：2012-01-31

申请号：US12464608

申请日：2009-05-12

Applicant: Yu-Min Lin ,  Dar-Zu Hsu ,  Hung-Lin Chen

Inventor： Yu-Min Lin ,  Dar-Zu Hsu ,  Hung-Lin Chen

IPC: H04J14/02

CPC classification number: H04L27/2662 ,  H04L27/2672 ,  H04L27/2675 ,  H04L27/2697

Abstract: A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation.

Abstract translation: 用于接收光正交频分复用（OFDM）信号的方法及其接收机可应用于光OFDM系统。 接收方法包括以下步骤。 光信号被转换为数字信号。 估计数字信号的符号边界。 根据符号边界去除数字信号的保护间隔，以产生电信号。 电信号以快速傅立叶变换（FFT）方式转换成多个频域子载波。 使用对应于相同符号周期的导频载波和频域子载波来估计定时偏移。 估计的符号边界用定时偏移补偿。 每个频域子载波包括多个导频载波信号。 通过接收方式，可以有效地估计出采用光纤色散引起的定时偏移补偿。

公开(公告)号：US20110198335A1

公开(公告)日：2011-08-18

申请号：US12725467

申请日：2010-03-17

Applicant: Yu-Min Lin

Inventor： Yu-Min Lin

IPC: H05B1/00 ,  F28F7/00

CPC classification number: H05B3/22 ,  F28D1/0477 ,  F28F1/22 ,  H01M10/613 ,  H01M10/615 ,  H01M10/637 ,  H01M10/647 ,  H01M10/6554 ,  H01M10/6556 ,  H01M10/6567 ,  H01M10/6571 ,  H01M10/658

Abstract: The present invention relates to a heating assembly, a heating device and an auxiliary cooling module for a battery. The heating assembly is connected to a battery and includes a heat-conducting element and a heating element. The heat-conducting element has at least one heat-absorbing portion and at least one heat-conducting portion. The heat-conducting portion is provided to correspond to the battery. The heating element has at least one first heating portion located to correspond to the heat-absorbing portion for heating the heat-absorbing portion. The other side of the heat-conducting element opposite to the battery is provided with a heat-insulating portion. The auxiliary cooling module is further provided with at least one cooling pipe in the heat-conducting element, thereby cooling the battery. With the heating assembly, the heating device, and the auxiliary cooling module of the present invention, the battery can be kept in a normal range of working temperature, so that the efficiency and lifetime of the battery can be increased greatly.

Abstract translation: 本发明涉及一种用于电池的加热组件，加热装置和辅助冷却模块。 加热组件连接到电池并且包括导热元件和加热元件。 导热元件具有至少一个吸热部分和至少一个导热部分。 导热部设置成对应于电池。 加热元件具有至少一个第一加热部分，其被定位成对应于用于加热吸热部分的吸热部分。 与电池相对的导热元件的另一侧设置有绝热部。 辅助冷却模块还在导热元件中设置有至少一个冷却管，从而冷却电池。 利用本发明的加热组件，加热装置和辅助冷却模块，电池可以保持在正常的工作温度范围内，从而可以大大提高电池的使用寿命。

公开(公告)号：US20100040182A1

公开(公告)日：2010-02-18

申请号：US12266530

申请日：2008-11-06

Applicant: Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

Inventor： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0041 ,  H04L7/0087 ,  H04Q11/0067 ,  H04Q2011/0079

Abstract: A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

Abstract translation: 提供了采用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中，使用锁相环（PLL）电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路，用于通过使用时钟信号检测接收数据信号的数据沿，并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路（DLL）电路耦合到锁相环电路和过采样相位选择电路，并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较，以便延迟 数据信号的数据相位延迟一个延迟时间，直到数据相位被锁定为时钟相位。

公开(公告)号：US07037816B2

公开(公告)日：2006-05-02

申请号：US10763643

申请日：2004-01-23

Applicant: Yu Min Lin ,  Ming-Fang Wang ,  Kun-Chih Lee ,  Ming-Ho Yang ,  Liang-Gi Yo ,  Shih-Chang Chen ,  Karen L. Mai

Inventor： Yu Min Lin ,  Ming-Fang Wang ,  Kun-Chih Lee ,  Ming-Ho Yang ,  Liang-Gi Yo ,  Shih-Chang Chen ,  Karen L. Mai

IPC: H01L21/4763

CPC classification number: H01L29/66833 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/10873 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating a portion of an integrated circuit on a semiconductor substrate. The method includes cleaning the surface of the substrate, and forming a thin insulate over the substrate. The method also includes depositing a high dielectric constant (high-k) material over the thin insulate, and then performing a hydrogen-based anneal on the high-k material. The method further includes performing an oxygen-based anneal on the high-k material, wherein the hydrogen-based and oxygen-based anneals occur sequentially.

Abstract translation: 一种在半导体衬底上制造集成电路的一部分的方法。 该方法包括清洗基底的表面，并在基底上形成薄的绝缘体。 该方法还包括在薄绝缘体上沉积高介电常数（高k）材料，然后在高k材料上进行氢基退火。 所述方法还包括对所述高k材料进行氧基退火，其中所述氢基和氧基退火依次发生。

公开(公告)号：US08599181B2

公开(公告)日：2013-12-03

申请号：US13227455

申请日：2011-09-07

Applicant: Yu-Min Lin ,  Hsin-Li Chen ,  Feng-Yuan Gan

Inventor： Yu-Min Lin ,  Hsin-Li Chen ,  Feng-Yuan Gan

IPC: G06F3/038

CPC classification number: H01L31/12 ,  G02F1/13338 ,  G02F2001/13312 ,  G06F3/0412 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2360/144 ,  H01L31/145 ,  H01L31/18

Abstract: A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

Abstract translation: 公开了一种光电检测器。 光检测器包括衬底，第一图案化半导体层，电介质层，图案化导电层，层间电介质，第二图案化半导体层，设置在层间电介质上的两个第一电极和设置在层间电介质上的两个第二电极 第二半导体层的部分。 具有第一掺杂区域和第二掺杂区域的第一图案化半导体层设置在晶体管区域上。 介电层设置成覆盖基板和第一半导体层，图案化的导电层设置在电介质层上，并且具有适于暴露第一掺杂区域和第二掺杂区域的至少两个开口的层间电介质是 被设置成覆盖电介质层。 第二图案化半导体层设置在光敏区域上，并且第一电极电连接到第一图案化半导体层。

公开(公告)号：US08415795B2

公开(公告)日：2013-04-09

申请号：US13089289

申请日：2011-04-18

Applicant: Yu-Min Lin ,  Chau-Jie Zhan ,  Su-Tsai Lu

Inventor： Yu-Min Lin ,  Chau-Jie Zhan ,  Su-Tsai Lu

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/345 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/14131 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81224 ,  H01L2224/81234 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81948 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225

Abstract: A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Abstract translation: 提供了一种半导体器件及其组装方法。 半导体器件包括芯片，载体，多个第一导电元件和多个第二导电元件。 芯片具有多个第一焊盘。 载体具有多个第二垫。 第二垫对应于第一垫。 每个第一导电元件设置在第一焊盘之一和第二焊盘中的一个之间。 每个第二导电元件设置在第一焊盘之一和第二焊盘中的一个之间。 第二导电元件的金属间化合物的体积比大于第一导电元件的金属间化合物的体积比。

公开(公告)号：US20120326238A1

公开(公告)日：2012-12-27

申请号：US13167738

申请日：2011-06-24

Applicant: Chin-Cheng Chien ,  Tzung-Ying Lee ,  Tsuo-Wen Lu ,  Shu-Yen Chan ,  Jei-Ming Chen ,  Yu-Min Lin ,  Chun-Wei Hsu

Inventor： Chin-Cheng Chien ,  Tzung-Ying Lee ,  Tsuo-Wen Lu ,  Shu-Yen Chan ,  Jei-Ming Chen ,  Yu-Min Lin ,  Chun-Wei Hsu

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/7833 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供其上具有第一区域和第二区域的衬底; 在基板上形成高k电介质层，阻挡层和第一金属层; 去除第二区域的第一金属层; 形成多晶硅层以覆盖第一区域的第一金属层和第二区域的阻挡层; 图案化多晶硅层，第一金属层，势垒层和高k电介质层，以在第一区域和第二区域中形成第一栅极结构和第二栅极结构; 以及在所述衬底中邻近所述第一栅极结构和所述第二栅极结构的两侧形成源极/漏极。