公开(公告)号：US20150371957A1

公开(公告)日：2015-12-24

申请号：US14555558

申请日：2014-11-26

申请人： Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

发明人： Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

摘要翻译： 半导体晶片具有多级结构，其能够阻止并包含切割期间产生的新生裂纹并且抑制水分渗透到模具的有源区域。 该晶片包括由划线所隔开的芯片区域阵列。 管芯区域包括有源区和围绕有源区的第一环。 第一环的一部分包括低k电介质材料。 第二环包括金属和层间电介质（ILD）材料的交替层叠。 围绕环的虚设金属区域包括堆叠的虚拟金属特征并围绕有源区域。 锯格过程控制（SGPC）特征的规则或不规则交错排列降低了切割时的机械应力。

公开(公告)号：US20150255443A1

公开(公告)日：2015-09-10

申请号：US14552442

申请日：2014-11-24

申请人： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

发明人： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L25/00

CPC分类号： H01L25/18 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49572 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15157 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

摘要翻译： 半导体封装具有引线框和功率管芯。 引线框架具有第一裸片，其具有完全穿过其中形成的空腔。 具有下表面的功率模具安装在第一模板上，使得下表面的第一部分使用无焊模片附着粘合剂附接到第一模板，并且下表面的第二部分， 没有附接到第一模板并且邻接形成在第一模板中的空腔，使得第二部分被暴露。

公开(公告)号：US20120128229A1

公开(公告)日：2012-05-24

申请号：US13293727

申请日：2011-11-10

申请人： Paul W. Sucro ,  Zhijie Wang ,  Deepak Sood ,  Peter M. Lister

发明人： Paul W. Sucro ,  Zhijie Wang ,  Deepak Sood ,  Peter M. Lister

IPC分类号： G06K9/00

CPC分类号： H01L24/78 ,  G06T7/0008 ,  G06T7/001 ,  G06T2207/20221 ,  G06T2207/30148 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/78 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method of imaging a feature of a semiconductor device is provided. The method includes the steps of: (a) imaging a first portion of a semiconductor device to form a first imaged portion; (b) imaging a subsequent portion of the semiconductor device to form a subsequent imaged portion; (c) adding the subsequent imaged portion to the first imaged portion to form a combined imaged portion; and (d) comparing the combined imaged portion to a reference image of a feature to determine a level of correlation of the combined imaged portion to the reference image.

摘要翻译： 提供了一种对半导体器件的特征进行成像的方法。 该方法包括以下步骤：（a）对半导体器件的第一部分进行成像以形成第一成像部分; （b）对所述半导体器件的后续部分进行成像以形成随后的成像部分; （c）将随后的成像部分添加到第一成像部分以形成组合的成像部分; 和（d）将组合的成像部分与特征的参考图像进行比较，以确定组合的成像部分与参考图像的相关程度。

公开(公告)号：US20110108967A1

公开(公告)日：2011-05-12

申请号：US12790999

申请日：2010-06-01

申请人： Zhigang BAI ,  Wei Min Chen ,  Zhijie Wang

发明人： Zhigang BAI ,  Wei Min Chen ,  Zhijie Wang

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/28

CPC分类号： H01L24/85 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor chip grid array package includes a die attach pad and a plurality of connector pads. A semiconductor die is mounted on the die attach pad, the semiconductor die having external connection terminals electrically connected respectively to the connector pads. An encapsulating material encapsulates the die and connector pads. A stud protrudes from each of the connector pads for providing an external electrical contact for the semiconductor chip grid array package. Each of the connector pads and respective studs are formed from an electrically conductive sheet. The connector pads have a thickness of at least 60% of the thickness of the conductive sheet and the respective studs have a thickness of no more than 40% of the thickness of the conductive sheet.

摘要翻译： 半导体芯片栅格阵列封装包括管芯附接焊盘和多个连接器焊盘。 半导体管芯安装在管芯安装焊盘上，半导体管芯具有分别电连接到连接器焊盘的外部连接端子。 封装材料封装管芯和连接器焊盘。 一个螺柱从每个连接器焊盘突出，用于为半导体芯片阵列封装提供外部电接触。 每个连接器焊盘和相应的螺柱由导电片形成。 连接器焊盘的厚度至少为导电片的厚度的60％，并且各个螺柱的厚度不超过导电片的厚度的40％。

公开(公告)号：US20080095497A1

公开(公告)日：2008-04-24

申请号：US11870404

申请日：2007-10-10

申请人： Xin Simon Luo ,  Pei Chuang Chen ,  Leming Wang ,  Zhijie Wang

发明人： Xin Simon Luo ,  Pei Chuang Chen ,  Leming Wang ,  Zhijie Wang

IPC分类号： G02B6/32

CPC分类号： G02B6/4204 ,  G02B6/32 ,  G02B6/4212

摘要： A coupling apparatus includes a lens disposed between a port, such as a photodetector, and a light source, such as a fiber. The lens is aligned such that light emitted from the light source is focused by the lens onto the port. Between the lens and light source and/or lens and port, a low contrast medium is disposed to reduce reflection that could degrade signal strength.

摘要翻译： 耦合装置包括设置在诸如光电检测器的端口和诸如光纤的光源之间的透镜。 镜头对齐，使得从光源发射的光被透镜聚焦到端口上。 在透镜和光源和/或透镜和端口之间，设置低对比度介质以减少可能降低信号强度的反射。

公开(公告)号：US09705850B2

公开(公告)日：2017-07-11

申请号：US14216332

申请日：2014-03-17

申请人： Dijiang Huang ,  Zhijie Wang

发明人： Dijiang Huang ,  Zhijie Wang

IPC分类号： H04L29/06 ,  H04L9/30 ,  G06F21/62

CPC分类号： H04L63/0428 ,  G06F21/6218 ,  H04L9/3073 ,  H04L63/06 ,  H04L63/102 ,  H04L2209/805

摘要： A new efficient framework based on a Constant-size Ciphertext Policy Comparative Attribute-Based Encryption (CCP-CABE) approach. CCP-CABE assists lightweight mobile devices and storing privacy-sensitive sensitive data into cloudbased storage by offloading major cryptography-computation overhead into the cloud without exposing data content to the cloud. CCP-CABE extends existing attribute-based data access control solutions by incorporating comparable attributes to incorporate more flexible security access control policies. CCP-CABE generates constant-size ciphertext regardless of the number of involved attributes, which is suitable for mobile devices considering their limited communication and storage capacities.

公开(公告)号：US20150294929A1

公开(公告)日：2015-10-15

申请号：US14552491

申请日：2014-11-25

申请人： Zhigang Bai ,  Zhijie Wang ,  Jinzhong Yao

发明人： Zhigang Bai ,  Zhijie Wang ,  Jinzhong Yao

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/565 ,  H01L21/4839 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15156 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor die package is assembled from a lead frame having lead fingers with a bonding end adjacent a die flag, and an elongate region extending away from the die flag. A semiconductor die is mounted on the die flag and electrodes of the semiconductor die are electrically connected to the bonding ends with bond wires. Each elongate region is bent into an external connector lead with mounting feet. The elongate region of each of the lead fingers protrudes from a housing formed from a mold compound. The mold compound extends from the housing to provide insulated support fingers molded to the external connector leads.

摘要翻译： 半导体管芯封装由具有引线指的引线框架组装，引线框具有邻近管芯标记的结合端，以及远离管芯标记延伸的细长区域。 半导体管芯安装在管芯标记上，半导体管芯的电极通过接合线与接合端电连接。 每个细长区域被弯曲成具有安装脚的外部连接器引线。 每个引线指的细长区域从由模具化合物形成的壳体突出。 模具化合物从壳体延伸，以提供模制到外部连接器引线的绝缘支撑指。

公开(公告)号：US08642395B2

公开(公告)日：2014-02-04

申请号：US12727258

申请日：2010-03-19

申请人： Zhe Li ,  Qingchun He ,  Guanhua Wang ,  Zhijie Wang ,  Nan Xu

发明人： Zhe Li ,  Qingchun He ,  Guanhua Wang ,  Zhijie Wang ,  Nan Xu

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L33/62

CPC分类号： H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/83099 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

摘要翻译： 芯片引线封装半导体器件的组装方法包括以下步骤：安装和锯切晶片以提供单独的半导体管芯; 在引线框上执行第一模制操作; 通过丝网印刷工艺在引线框架上沉积环氧树脂; 在引线框架上用环氧树脂将一个单模模具附着在模具附着在室温下进行; 并在烘箱中固化环氧树脂。 吞吐量改进可归因于不包括热模附着过程。 可以进行可选的等离子体清洗步骤，这大大提高了引线接合质量和第二成型质量。 此外，由于在形成环氧树脂之前进行第一次成型操作以避免环氧树脂悬挂在空气中的问题，所以避免了环氧树脂和模具之间的脱层危险。

公开(公告)号：US08198737B2

公开(公告)日：2012-06-12

申请号：US12510274

申请日：2009-07-28

申请人： Changliang Zhang ,  Yingwei Jiang ,  Zhijie Wang ,  Wei Xiao

发明人： Changliang Zhang ,  Yingwei Jiang ,  Zhijie Wang ,  Wei Xiao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48489 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49175 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2224/78 ,  H01L2924/00

摘要： A method of forming a wire bond in a semiconductor device includes forming a first bump of a first composition proximate to a probe mark on a bond pad. A second bump of the first composition is formed adjacent to the first bump such that the first and second bumps are formed away from the probe mark. A wire of a second composition that is harder than the first composition is attached on top of the first and second bumps to form an interconnection.

摘要翻译： 在半导体器件中形成引线接合的方法包括在接合焊盘上形成靠近探针标记的第一组合物的第一凸点。 第一组合物的第二凸起形成为与第一凸起相邻，使得第一和第二凸块形成为远离探针标记。 比第一组合物硬的第二组合物的导线附接在第一和第二凸块的顶部上以形成互连。

公开(公告)号：US20120018858A1

公开(公告)日：2012-01-26

申请号：US13092162

申请日：2011-04-22

申请人： Wei Min Chen ,  Zhigang Bai ,  Zhijie Wang

发明人： Wei Min Chen ,  Zhigang Bai ,  Zhijie Wang

IPC分类号： H01L23/552 ,  H01L21/56

CPC分类号： H01L23/552 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of assembling an integrated circuit (IC) device includes the steps of providing a lead frame or substrate panel, attaching a semiconductor die to the lead frame or substrate panel and electrically coupling the die to the lead frame or substrate panel. The method further includes encapsulating the die with a first encapsulant, and the encapsulating the first encapsulant with a second encapsulant where the second encapsulant includes a material that provides electromagnetic shielding.

摘要翻译： 一种组装集成电路（IC）器件的方法包括以下步骤：提供引线框架或衬底面板，将半导体管芯附接到引线框架或衬底面板，并将管芯电耦合到引线框架或衬底面板。 该方法还包括用第一密封剂封装管芯，并用第二密封剂封装第一密封剂，其中第二密封剂包括提供电磁屏蔽的材料。