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    Silicon gate CCD structure
    1.
    发明授权
    Silicon gate CCD structure 失效
    硅栅CCD结构

    公开(公告)号：US4027382A

    公开(公告)日：1977-06-07

    申请号：US691657

    申请日：1976-06-01

    申请人： Al F. Tasch, Jr. ,  Robert C. Frye

    发明人： Al F. Tasch, Jr. ,  Robert C. Frye

    IPC分类号： H01L21/285 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/768 ,  B01J17/00

    CPC分类号： H01L29/66954 ,  H01L21/28525 ,  H01L21/823406 ,  H01L29/1062 ,  H01L29/76875

    摘要： Process for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

    摘要翻译： 制造具有边缘相邻电极并利用单一绝缘材料的两相电荷耦合器件（CCD）的工艺。 偏移自对准技术用于实现离子注入势阱或势垒区域的精确定位，以实现具有小位或电荷存储元件尺寸的CCD的每个栅极区域中的势阱（或阈值电压）所需的不对称性，导致 具有高填充密度的结构。 描述了表面和掩埋通道结构的制造。

    CCD structures with surface potential asymmetry beneath the phase electrodes
    2.
    发明授权
    CCD structures with surface potential asymmetry beneath the phase electrodes 失效
    相位电极下面具有表面电位不对称的CCD结构

    公开(公告)号：US4167017A

    公开(公告)日：1979-09-04

    申请号：US853380

    申请日：1977-11-04

    申请人： Al F. Tasch, Jr. ,  Robert C. Frye

    发明人： Al F. Tasch, Jr. ,  Robert C. Frye

    IPC分类号： H01L21/339 ,  H01L29/10 ,  H01L29/768 ,  H01L29/78 ,  G11C19/28 ,  H01L29/04

    CPC分类号： H01L29/66954 ,  H01L29/1062 ,  H01L29/76841

    摘要： Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

    摘要翻译： 制造具有边缘相邻电极并利用单一绝缘材料的两相电荷耦合器件（CCD）的工艺。 偏移自对准技术用于实现离子注入势阱或势垒区域的精确定位，以实现具有小位或电荷存储元件尺寸的CCD的每个栅极区域中的势阱（或阈值电压）所需的不对称性，导致 具有高填充密度的结构。 描述了表面和掩埋通道结构的制造。

    Silicon gate CCD structure
    3.
    发明授权
    Silicon gate CCD structure 失效
    硅栅CCD结构

    公开(公告)号：US4035906A

    公开(公告)日：1977-07-19

    申请号：US737648

    申请日：1976-11-01

    申请人： Al F. Tasch ,  Robert C. Frye

    发明人： Al F. Tasch ,  Robert C. Frye

    IPC分类号： H01L21/285 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/768 ,  B01J17/00

    CPC分类号： H01L29/66954 ,  H01L21/28525 ,  H01L21/823406 ,  H01L29/1062 ,  H01L29/76875 ,  Y10S148/053 ,  Y10S148/143

    摘要： Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

    摘要翻译： 制造具有边缘相邻电极并利用单一绝缘材料的两相电荷耦合器件（CCD）的工艺。 偏移自对准技术用于实现离子注入势阱或势垒区域的精确定位，以实现具有小位或电荷存储元件尺寸的CCD的每个栅极区域中的势阱（或阈值电压）所需的不对称性，导致 具有高填充密度的结构。 描述了表面和掩埋通道结构的制造。

    Silicon gate ccd structure
    4.
    发明授权
    Silicon gate ccd structure 失效
    硅栅ccd结构

    公开(公告)号：US4027381A

    公开(公告)日：1977-06-07

    申请号：US691656

    申请日：1976-06-01

    申请人： Al F. Tasch, Jr. ,  Robert C. Frye

    发明人： Al F. Tasch, Jr. ,  Robert C. Frye

    IPC分类号： H01L21/285 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/768 ,  B01J17/00

    CPC分类号： H01L29/66954 ,  H01L21/28525 ,  H01L21/823406 ,  H01L29/1062 ,  H01L29/76875

    摘要： Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

    摘要翻译： 制造具有边缘相邻电极并利用单一绝缘材料的两相电荷耦合器件（CCD）的工艺。 偏移自对准技术用于实现离子注入势阱或势垒区域的精确定位，以实现具有小位或电荷存储元件尺寸的CCD的每个栅极区域中的势阱（或阈值电压）所需的不对称性，导致 具有高填充密度的结构。 描述了表面和掩埋通道结构的制造。

    Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD)
    6.
    发明授权
    Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD) 有权
    在集成无源器件（IPD）中形成电容器和互连顶电极的方法

    公开(公告)号：US08399990B2

    公开(公告)日：2013-03-19

    申请号：US13355354

    申请日：2012-01-20

    申请人： Yaojian Lin ,  Robert C. Frye

    发明人： Yaojian Lin ,  Robert C. Frye

    IPC分类号： H01L23/48

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

    摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

    摘要翻译： 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

    Semiconductor Device and Method of Shunt Test Measurement for Passive Circuits
    8.
    发明申请
    Semiconductor Device and Method of Shunt Test Measurement for Passive Circuits 有权
    半导体器件和无源电路并联测试测量方法

    公开(公告)号：US20100001268A1

    公开(公告)日：2010-01-07

    申请号：US12167039

    申请日：2008-07-02

    申请人： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

    发明人： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

    IPC分类号： H01L23/58 ,  H01L21/02

    CPC分类号： H01L22/34 ,  H01L23/64 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/3011 ,  H01L2924/00014

    摘要： A semiconductor device has an inductor and capacitor formed on the substrate. The inductor and capacitor are electrically connected in series. The inductor is a coiled conductive layer. The capacitor has first and second conductive layers separated by an insulating layer. A first test pad and second test pad are formed on the substrate. A terminal of the inductor is coupled to the first and second test pads. A third test pad and fourth test pad are formed on the substrate. A terminal of the capacitor is coupled to the third and fourth test pads such that the inductor and capacitor are connected in shunt between the first and second test pads and the third and fourth test pads. An electrical characteristic of the inductor and capacitor such that resonant frequency and quality factor are tested using a two-port shunt measurement which negates series resistance of test probes.

    摘要翻译： 半导体器件具有形成在衬底上的电感器和电容器。 电感器和电容器串联电连接。 电感器是线圈导电层。 该电容器具有被绝缘层隔开的第一和第二导电层。 在基板上形成第一测试焊盘和第二测试焊盘。 电感器的端子耦合到第一和第二测试焊盘。 在基板上形成第三测试焊盘和第四测试焊盘。 电容器的端子耦合到第三和第四测试焊盘，使得电感器和电容器在第一和第二测试焊盘与第三和第四测试焊盘之间分流连接。 电感器和电容器的电气特性使得谐振频率和品质因数使用双端口分流测量进行测试，这样可以消除测试探针的串联电阻。

    Temporary connections for fast electrical access to electronic devices
    9.
    发明授权
    Temporary connections for fast electrical access to electronic devices 失效
    用于快速电气接入电子设备的临时连接

    公开(公告)号：US5481205A

    公开(公告)日：1996-01-02

    申请号：US344393

    申请日：1994-11-23

    申请人： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

    发明人： Robert C. Frye ,  Maureen Y. Lau ,  King L. Tai

    IPC分类号： H01L21/66 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  H01L27/10 ,  H05K3/32 ,  G01R1/06 ,  H01L23/48

    CPC分类号： H05K3/325 ,  G01R1/07307 ,  G01R1/06738 ,  H01L2924/0002

    摘要： A given testing substrate for fast-testing many integrated-circuit electronic devices, one after the other, has a set of mutually insulated collated wiring areas that can be aligned with solder-bump I/O pads of the electronic devices. At the surface of each of the corrugated areas is located a layer that is an electrically conductive durable oxide, or that is itself durable, electrically conductive, and non-oxidizable. During testing, the solder-bump I/O pads of the electronic device being tested are aligned with and pressed against the corrugated wiring areas of the given substrate. Alternatively, the electronic devices being of the electrically programmable variety, such as EPROMs, programming voltages can be delivered to each of the devices, one after the other, through the corrugated wiring areas of a single substrate.

    摘要翻译： 给定的用于快速测试许多集成电路电子器件的测试基板，一个接一个地具有一组可以与电子器件的焊料凸块I / O焊盘对准的相互绝缘的整理布线区域。 在每个波纹区域的表面上设置有导电耐用氧化物的层，或者其本身是耐用的，导电的和不可氧化的。 在测试期间，正在测试的电子器件的焊料凸块I / O焊盘与给定衬底的波纹布线区域对准并压紧。 或者，可以通过单个基板的波纹布线区域，一个接一个地将诸如EPROM的编程电压的电可编程品种的电子装置传送到每个装置。

    Semiconductor device and method of forming RF balun having reduced capacitive coupling and high CMRR
    10.
    发明授权
    Semiconductor device and method of forming RF balun having reduced capacitive coupling and high CMRR 有权
    形成具有降低的电容耦合和高CMRR的RF平衡 - 不平衡变换器的半导体器件和方法

    公开(公告)号：US08981866B2

    公开(公告)日：2015-03-17

    申请号：US13571068

    申请日：2012-08-09

    申请人： Robert C. Frye ,  Kai Liu

    发明人： Robert C. Frye ,  Kai Liu

    IPC分类号： H03H7/42 ,  H01L23/522 ,  H01P5/10

    CPC分类号： H01L23/5227 ,  H01L23/5223 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10T29/41 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace.

    摘要翻译： 半导体器件具有在衬底上形成的RF平衡 - 不平衡变压器。 RF平衡 - 不平衡变压器包括缠绕以显示感应特性的第一导电迹线，其中第一端耦合到半导体器件的第一端子，第二端耦合到半导体器件的第二端子。 第一电容器耦合在第一导电迹线的第一和第二端之间。 第二导电迹线被卷绕以呈现感应特性，其中第一端耦合到半导体器件的第三端子，第二端耦合到半导体器件的第四端子。 第一导电迹线完全在第二导电迹线内形成。 第一导电迹线和第二导电迹线可以具有由50微米分开的椭圆形，圆形或多边形形状。 第二电容器耦合在第二导电迹线的第一端和第二端之间。