公开(公告)号：US20080166525A1

公开(公告)日：2008-07-10

申请号：US11963487

申请日：2007-12-21

申请人： Bart Swinnen ,  Eric Beyne

发明人： Bart Swinnen ,  Eric Beyne

IPC分类号： B32B37/26 ,  B32B7/06 ,  B44C1/22 ,  B05D7/24

CPC分类号： H01L21/6835 ,  H01L2221/6834 ,  Y10T428/24 ,  Y10T428/24628

摘要： A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

摘要翻译： 公开了一种通过诸如胶层之类的粘结剂粘接两个元件的方法，其中粘合剂是可去除的，并且其中在粘合剂和至少一个元件之间施加牺牲层，该牺牲层可相对于 到那个元素 根据实施例，元件包括结合到载体晶片的管芯或衬底。 模具或基底和载体的性质和类型可以在本发明的实施例的范围内变化。 还公开了可通过本发明的方法获得的复合基材。

公开(公告)号：US20060068567A1

公开(公告)日：2006-03-30

申请号：US11234835

申请日：2005-09-23

申请人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

发明人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/3043

摘要： The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

公开(公告)号：US08809188B2

公开(公告)日：2014-08-19

申请号：US12885311

申请日：2010-09-17

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

IPC分类号： H01L21/44

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

摘要翻译： 公开了一种通过衬底通孔制造的方法。 在一个方面，通孔从衬底的背面蚀刻到浅沟槽隔离（STI）或预金属电介质叠层（PMD）。 制造金属1接触焊盘和贯通晶片通孔之间的额外接触，以实现贯穿晶片通孔和半导体芯片的后端行之间的接触。

公开(公告)号：US20110089572A1

公开(公告)日：2011-04-21

申请号：US12885311

申请日：2010-09-17

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

摘要翻译： 公开了一种通过衬底通孔制造的方法。 在一个方面，通孔从衬底的背面蚀刻到浅沟槽隔离（STI）或预金属电介质叠层（PMD）。 制造金属1接触焊盘和贯通晶片通孔之间的额外接触，以实现贯穿晶片通孔和半导体芯片的后端行之间的接触。

公开(公告)号：US07795113B2

公开(公告)日：2010-09-14

申请号：US11963487

申请日：2007-12-21

申请人： Bart Swinnen ,  Eric Beyne

发明人： Bart Swinnen ,  Eric Beyne

IPC分类号： H01L21/46

CPC分类号： H01L21/6835 ,  H01L2221/6834 ,  Y10T428/24 ,  Y10T428/24628

摘要： A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

摘要翻译： 公开了一种通过诸如胶层之类的粘结剂粘接两个元件的方法，其中粘合剂是可去除的，并且其中在粘合剂和至少一个元件之间施加牺牲层，该牺牲层可相对于 到那个元素 根据实施例，元件包括结合到载体晶片的管芯或衬底。 模具或基底和载体的性质和类型可以在本发明的实施例的范围内变化。 还公开了可通过本发明的方法获得的复合基材。

公开(公告)号：US07566634B2

公开(公告)日：2009-07-28

申请号：US11234835

申请日：2005-09-23

申请人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

发明人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/3043

摘要： The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

摘要翻译： 本发明涉及一种用于从诸如晶片或基板上的层的层叠单片化芯片的方法。 层叠层包括在衬底层上的前端（FEOL）层，衬底层具有第一表面和第二表面。 FEOL位于第一表面的顶部，并且后端（BEOL）层位于FEOL的顶部。 该方法包括通过BEOL，通过FEOL蚀刻单个沟槽并且至少部分地穿过衬底层，在设置有单个沟槽的堆叠上沉积钝化层，由此蚀刻的单个化沟槽的侧壁至少部分钝化。 执行切割，例如刀片切割，激光切割或沟槽蚀刻切割，从堆叠层释放芯片。

公开(公告)号：US08450825B2

公开(公告)日：2013-05-28

申请号：US12848057

申请日：2010-07-30

申请人： Paresh Limaye ,  Jan Vanfleteren ,  Eric Beyne

发明人： Paresh Limaye ,  Jan Vanfleteren ,  Eric Beyne

IPC分类号： H01L23/36

CPC分类号： H01L23/49833 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package is disclosed. In one aspect, the package includes a base frame and a wiring substrate mounted on the base frame. The base frame has two pieces made of a material with respectively a first and a second coefficient of thermal expansion and connected to each other via resilient connecting structures. The wiring substrate has electric wiring tracks providing the electric connection between first and second bond pads, provided for being electrically connected to bond pads on respectively a die and a printed wiring board. The electrical wiring tracks have flexible parts provided to expand and contract along with the resilient connecting structures.

摘要翻译： 公开了半导体封装。 在一个方面中，包装包括安装在基架上的基架和布线基板。 基座框架具有由具有第一和第二热膨胀系数的材料制成的两个部件，并通过弹性连接结构相互连接。 布线基板具有提供第一和第二接合焊盘之间的电连接的电线路轨道，提供用于分别电连接到管芯和印刷线路板上的接合焊盘。 电线轨道具有设置成与弹性连接结构一起膨胀和收缩的柔性部分。

公开(公告)号：US20120013022A1

公开(公告)日：2012-01-19

申请号：US13183315

申请日：2011-07-14

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Eric Beyne

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

摘要翻译： 公开了超低电容互连结构，优选地通过硅通孔（TSV）互连和用于制造所述互连的方法。 该制造方法包括以下步骤：提供具有第一主表面的基底，从第一主表面至少产生一个中空的沟槽状结构，所述沟槽状结构围绕基底材料的内柱结构，沉积介电衬垫 其在第一主表面处夹紧所述中空沟槽状结构，使得在中空沟槽状结构的中心产生气隙，并进一步产生TSV孔并至少部分地用导电材料填充TSV孔。

公开(公告)号：US20110233792A1

公开(公告)日：2011-09-29

申请号：US13051357

申请日：2011-03-18

申请人： Wenqi Zhang ,  Eric Beyne

发明人： Wenqi Zhang ,  Eric Beyne

IPC分类号： H01L23/48 ,  B23K31/02

CPC分类号： H01L25/50 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32507 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83099 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： A device and a method for realizing reliable electrical contacts at low temperature and low pressure between conducting materials on, for example, different substrates are disclosed. In one aspect, a rough and brittle intermetallic layer is formed on a conducting material on a first substrate. A soft solder material layer on the other substrate is used for contacting the brittle and rough intermetallic layer that will break. As the solder material is relatively soft, contact between the broken intermetallic layer and the solder material can be realized over a large portion of the surface area. At that stage, a second intermetallic layer is formed between the solder material and the first intermetallic layer realizing electrical contact.

摘要翻译： 公开了一种在例如不同基板之间的导电材料之间在低温低压下实现可靠​​的电接触的装置和方法。 一方面，在第一基板上的导电材料上形成粗糙且脆性的金属间层。 另一个基板上的软焊料层用于接触将会断裂的脆性和粗糙金属间层。 由于焊料材料相对较软，可以在大部分表面积上实现断裂的金属间层与焊料之间的接触。 在该阶段，在焊料和第一金属间层之间形成第二金属间层，实现电接触。

公开(公告)号：US07737552B2

公开(公告)日：2010-06-15

申请号：US12126766

申请日：2008-05-23

申请人： Eric Beyne

发明人： Eric Beyne

IPC分类号： H01L23/34 ,  H01L21/00 ,  H01R12/16

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/563 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/11005 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00012

摘要： A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

摘要翻译： 描述用于结合元件的装置和方法。 在第一元件的主表面上产生第一焊球。 在第二元件的主表面上产生第二焊球。 在第一焊球和第二焊球之间提供接触。 第一和第二元件通过施加回流作用而结合，由此焊球熔化并形成接合的焊球结构。 在接合之前，第一焊球侧向嵌入在第一非导电材料层中，并且第二焊球侧向嵌入第二非导电材料层中，使得第一焊球的上部和 第二焊球的上部不被非导电材料覆盖。 在接合之前，在嵌入的第一或第二焊球的一个或两个上施加第三焊料体积。