公开(公告)号：US20180061811A1

公开(公告)日：2018-03-01

申请号：US15373494

申请日：2016-12-09

申请人： ChipMOS Technologies Inc.

发明人： Geng-Shin Shen ,  Ching-Chen Tu ,  Tzu-Sheng Wu ,  Chun-Chen Lin ,  Hui-Wen Yeh

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip includes a first active surface having a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone. The second chip is flipped on the chip bonding zone. The first conductive bumps are disposed on the first outer pads. The second conductive bumps are disposed between the first inner pads of the first chip and a plurality of second pads of the second chip. The underfill is disposed on the first active surface and covers the second conductive bumps, at least a part of each second chip lateral and at least a part of each first conductive bump. Multiple semiconductor package manufacturing methods are further provided.

公开(公告)号：US08872336B2

公开(公告)日：2014-10-28

申请号：US13654710

申请日：2012-10-18

申请人： Chipmos Technologies Inc.

发明人： Geng-Shin Shen ,  Chung-Pang Chi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

摘要翻译： 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括半导体衬底，衬垫，钝化层和图案化绝缘层。 图案化的绝缘层设置在钝化层上，并且部分地并且直接覆盖焊盘的第一开口以露出第二开口。 导电结构包括凹凸金属（UBM）层和导电凸块。 UBM层设置在由图案化的绝缘层限定的第二开口中，并且电连接到焊盘。 导电凸块设置在UBM层上并与UBM层电连接。 导电凸块的上表面大于图案化绝缘层的上表面，而布置在第二开口中的导电凸块的部分被UBM层覆盖。

公开(公告)号：US08809088B2

公开(公告)日：2014-08-19

申请号：US13801255

申请日：2013-03-13

申请人： Chipmos Technologies Inc.

发明人： Geng-Shin Shen ,  Ya Chi Chen ,  I-Hsin Mao

IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L23/00

CPC分类号： H01L27/14636 ,  H01L21/563 ,  H01L23/00 ,  H01L23/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14683 ,  H01L27/14687 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/29011 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14335 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2924/00

摘要： A structure of stacking chips and a method for manufacturing the structure of stacking chips are provided. A wafer with optical chips and a glass substrate with signal processing chips are stacked with each other, and then subjected to ball mounting and die sawing to form the stacked packaging structure. The optical chips and the signal processing chips form the electrical connection on the surface of the glass substrate via the through holes thereof.

摘要翻译： 提供堆叠芯片的结构以及堆叠芯片的结构的制造方法。 具有光学芯片的晶片和具有信号处理芯片的玻璃基板彼此堆叠，然后进行球安装和模切以形成堆叠的封装结构。 光学芯片和信号处理芯片通过其通孔在玻璃基板的表面上形成电连接。

公开(公告)号：US09159685B2

公开(公告)日：2015-10-13

申请号：US14494026

申请日：2014-09-23

申请人： CHIPMOS TECHNOLOGIES INC.

发明人： Geng-Shin Shen ,  Chung-Pang Chi

IPC分类号： H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

摘要翻译： 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括半导体衬底，衬垫，钝化层和图案化绝缘层。 图案化的绝缘层设置在钝化层上，并且部分地并且直接覆盖焊盘的第一开口以露出第二开口。 导电结构包括凹凸金属（UBM）层和导电凸块。 UBM层设置在由图案化的绝缘层限定的第二开口中，并且电连接到焊盘。 导电凸块设置在UBM层上并与UBM层电连接。 导电凸块的上表面大于图案化绝缘层的上表面，而布置在第二开口中的导电凸块的部分被UBM层覆盖。

公开(公告)号：US08786082B2

公开(公告)日：2014-07-22

申请号：US13671202

申请日：2012-11-07

申请人： Chipmos Technologies Inc.

发明人： Geng-Shin Shen

IPC分类号： H01L23/48

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05013 ,  H01L2224/05022 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/14104 ,  H01L2224/1412 ,  H01L2224/14153 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

摘要翻译： 提供半导体结构。 半导体结构包括衬底，至少两个焊盘，钝化层，至少两个凸块下金属化（UBM）层和至少两个凸块。 焊盘沿着第一方向在基板上彼此相邻设置。 钝化层覆盖基板和每个焊盘的周边上表面以限定开口。 每个开口限定沿着第二方向的开口凸起。 开口突起彼此相邻设置，但彼此不重叠。 此外，第一方向垂直于第二方向。 UBM层设置在相应的开口上，凸块分别设置在相应的UBM层上。 利用上述布置，本发明的半导体结构的每个凸起的宽度可以被加宽而不受凸点间距的限制。

公开(公告)号：US08962395B2

公开(公告)日：2015-02-24

申请号：US13918518

申请日：2013-06-14

申请人： ChipMOS Technologies Inc.

发明人： Geng-Shin Shen

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/495

CPC分类号： H01L24/11 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16245 ,  H01L2224/8191 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

摘要翻译： 本发明提供一种四平坦无铅（QFN）封装，其包括芯片，引线框架，多个复合凸块和密封剂。 芯片具有多个焊盘，引线框架具有多个引线。 多个复合凸块中的每一个具有第一导电层和第二导电层。 第一导电层电连接在一个焊盘和第二导电层之间，并且第二导电层电连接在第一导电层和引线之一之间。 密封剂封装芯片，引线和复合凸块。 由此，在提供芯片接合到引线框架之前，在引线框架的引线的间隙之间形成具有复合凸块和半固化密封剂的QFN封装。