公开(公告)号：US08258615B2

公开(公告)日：2012-09-04

申请号：US12389388

申请日：2009-02-20

申请人： Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li

发明人： Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li

IPC分类号： H01L23/498

CPC分类号： H01L23/642 ,  H01L23/3114 ,  H01L23/367 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.

摘要翻译： 本发明提供能够消除半导体器件内的半导体管芯的电压（IR）下降的半导体器件以及半导体器件的制造方法。 半导体器件包括半导体管芯，并且半导体管芯包括第一表面区域，潜在地相当于彼此的多个第一焊盘，钝化层，多个第一开口和第一导电介质层。 钝化层设置在多个第一焊盘上。 多个第一开口形成在钝化层上，并用于暴露多个第一焊盘。 第一导电介质层形成在第一表面区域上，用于实现多个第一开口以连接多个第一焊盘。

公开(公告)号：US20100171211A1

公开(公告)日：2010-07-08

申请号：US12350208

申请日：2009-01-07

申请人： Che-Yuan Jao ,  Sheng-Ming Chang

发明人： Che-Yuan Jao ,  Sheng-Ming Chang

IPC分类号： H01L23/488

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/552 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is provided by the present invention. The semiconductor device includes a semiconductor die, and the semiconductor die includes a die core having at least two bond pads with voltage level equivalent to each other and electrically connected to each other via at least a bond wire, and an input/output (I/O) periphery. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.

摘要翻译： 本发明提供一种半导体器件。 所述半导体器件包括半导体管芯，并且所述半导体管芯包括具有至少两个接合焊盘的芯片，所述至少两个接合焊盘的电压水平彼此相等并且至少通过接合线彼此电连接，以及输入/输出（I / O）周边。 本发明的半导体器件能够以低成本解决半导体管芯的IR下降。

公开(公告)号：US08525310B2

公开(公告)日：2013-09-03

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US07880297B2

公开(公告)日：2011-02-01

申请号：US12116969

申请日：2008-05-08

申请人： Che-Yuan Jao ,  Sheng-Ming Chang ,  Ching-Chih Li

发明人： Che-Yuan Jao ,  Sheng-Ming Chang ,  Ching-Chih Li

IPC分类号： H01L23/12 ,  H01L23/06 ,  H01L23/10 ,  H01L23/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01004

摘要： A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member.

摘要翻译： 半导体芯片包括安装在封装基板上的管芯。 芯片包括半导体衬底; 半导体衬底上的金属间介电层; 金属互连级别，其中在金属互连的级别中形成至少两个潜在的等效金属迹线; 设置在所述两个金属迹线上的钝化层，其中在所述钝化层中形成两个开口以暴露所述两个金属迹线的部分; 外部安装在两个开口之间的钝化层上的导电构件; 以及形成在导电构件上的再分布层。

公开(公告)号：US20090224393A1

公开(公告)日：2009-09-10

申请号：US12389388

申请日：2009-02-20

申请人： Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li

发明人： Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li

IPC分类号： H01L23/498 ,  H01L21/50 ,  H01L29/92

CPC分类号： H01L23/642 ,  H01L23/3114 ,  H01L23/367 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.

摘要翻译： 本发明提供能够消除半导体器件内的半导体管芯的电压（IR）下降的半导体器件以及半导体器件的制造方法。 半导体器件包括半导体管芯，并且半导体管芯包括第一表面区域，潜在地相当于彼此的多个第一焊盘，钝化层，多个第一开口和第一导电介质层。 钝化层设置在多个第一焊盘上。 多个第一开口形成在钝化层上，并用于暴露多个第一焊盘。 第一导电介质层形成在第一表面区域上，用于实现多个第一开口以连接多个第一焊盘。

公开(公告)号：US20090166849A1

公开(公告)日：2009-07-02

申请号：US12116969

申请日：2008-05-08

申请人： Che-Yuan Jao ,  Sheng-Ming Chang ,  Ching-Chih Li

发明人： Che-Yuan Jao ,  Sheng-Ming Chang ,  Ching-Chih Li

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/01004

摘要： A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member.

摘要翻译： 半导体芯片包括安装在封装基板上的管芯。 芯片包括半导体衬底; 半导体衬底上的金属间介电层; 金属互连级别，其中在金属互连的级别中形成至少两个潜在的等效金属迹线; 设置在所述两个金属迹线上的钝化层，其中在所述钝化层中形成两个开口以暴露所述两个金属迹线的部分; 外部安装在两个开口之间的钝化层上的导电构件; 以及形成在导电构件上的再分布层。

公开(公告)号：US20110248394A1

公开(公告)日：2011-10-13

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US20110241206A1

公开(公告)日：2011-10-06

申请号：US13164779

申请日：2011-06-21

申请人： Che-Yuan Jao ,  Sheng-Ming Chang

发明人： Che-Yuan Jao ,  Sheng-Ming Chang

IPC分类号： H01L25/07 ,  H01L23/49 ,  H01L23/492

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/552 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is provided by the present invention. The semiconductor device includes a first semiconductor die comprising at least a first bond pad; and a second semiconductor die comprising at least a second bond pad with voltage level equivalent to the first bond pad of the first semiconductor die; wherein the first bond pad of the first semiconductor die is electrically connected to the second bond pad of the second semiconductor die via at least a bond wire. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括至少包括第一接合焊盘的第一半导体管芯; 以及第二半导体管芯，其包括至少第二接合焊盘，其具有与所述第一半导体管芯的所述第一接合焊盘相当的电压电平; 其中所述第一半导体管芯的所述第一接合焊盘至少通过接合线电连接到所述第二半导体管芯的所述第二接合焊盘。 本发明的半导体器件能够以低成本解决半导体管芯的IR下降。

公开(公告)号：US20090187874A1

公开(公告)日：2009-07-23

申请号：US12015627

申请日：2008-01-17

申请人： Mao-Lin Wu ,  Shih-Hung Lin ,  Hua Wu ,  Che Yuan Jao ,  Ching-Chih Li ,  Sheng-Ming Chang

发明人： Mao-Lin Wu ,  Shih-Hung Lin ,  Hua Wu ,  Che Yuan Jao ,  Ching-Chih Li ,  Sheng-Ming Chang

IPC分类号： G06F17/50

CPC分类号： H05K1/0216 ,  H01R12/79 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/10166 ,  H05K2201/10689

摘要： A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path.

摘要翻译： 提供电路和电路设计方法。 该电路在第一电源电压和接地电压之间工作。 该电路包括至少一个低速电路路径和至少一个高速电路路径。 低速电路路径调整第一电源电压或接地电压时的电压电平。 低速电路路径提供第一返回路径并隔离高速电路路径上的信号的不需要的噪声信号。

公开(公告)号：US08595504B2

公开(公告)日：2013-11-26

申请号：US12190238

申请日：2008-08-12

申请人： Shih-I Huang ,  Shiuh-Pyng Shieh ,  Sheng-Ming Chang ,  Chi-Wei Wang

发明人： Shih-I Huang ,  Shiuh-Pyng Shieh ,  Sheng-Ming Chang ,  Chi-Wei Wang

IPC分类号： H04L9/00

CPC分类号： H04L9/3236 ,  H04L9/3247 ,  H04L2209/805

摘要： A method for authenticating a message in a network is provided. The method includes a step of generating, in a sink device, a private key and a public key. The private key includes a plurality of sub-private keys. The method further includes a step of generating, in the sink device, a signature for the message. The signature includes a sub-private key and an authentication path associated with the sub-private key in a hash tree. The hash tree is constructed during the generation of the sub-public keys.

摘要翻译： 提供了一种用于在网络中验证消息的方法。 该方法包括在宿设备中生成私钥和公钥的步骤。 私钥包括多个子私钥。 该方法还包括在宿设备中生成消息的签名的步骤。 签名包括子私钥和与散列树中的子私钥相关联的认证路径。 在生成子公钥期间构建散列树。