公开(公告)号：US08609540B2

公开(公告)日：2013-12-17

申请号：US13164448

申请日：2011-06-20

Applicant: Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L21/32

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US09634412B2

公开(公告)日：2017-04-25

申请号：US13183920

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Craig Mitchell

IPC: H05K1/09 ,  H01R13/03 ,  H05K3/40 ,  H05K3/28

CPC classification number: H01R13/03 ,  H05K1/09 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/09745 ,  Y10T29/49155

Abstract: Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use.

公开(公告)号：US09142508B2

公开(公告)日：2015-09-22

申请号：US13170095

申请日：2011-06-27

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

Abstract translation: 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。

公开(公告)号：US08692118B2

公开(公告)日：2014-04-08

申请号：US13168675

申请日：2011-06-24

Applicant: Cyprian Uzoh ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Craig Mitchell

IPC: H01B5/00

CPC classification number: H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45605 ,  H01L2224/45609 ,  H01L2224/45611 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/45887 ,  H01L2224/45893 ,  H01L2224/48 ,  H01L2224/85207 ,  H01L2924/01015 ,  H01L2924/10253 ,  Y10T29/49117 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01006

Abstract: A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.

Abstract translation: 公开了一种可被配置用于半导体器件的导线结构。 线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。 包层可以是导体。 在各个方面，包覆层和芯具有不同的晶粒尺寸。 芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。 包覆层可以是在其厚度上具有不同浓度的次要组分的合金。 还公开了形成线结构的方法。

公开(公告)号：US20120326313A1

公开(公告)日：2012-12-27

申请号：US13170095

申请日：2011-06-27

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

Abstract translation: 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。

公开(公告)号：US20130014978A1

公开(公告)日：2013-01-17

申请号：US13183870

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC: H05K1/09 ,  B05D1/36 ,  B05D5/12

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.

Abstract translation: 用于电气应用的阻隔层。 在一些实施例中，阻挡层是层压阻挡层。 在一些实施例中，阻挡层包括梯度阻挡层。

公开(公告)号：US20120319282A1

公开(公告)日：2012-12-20

申请号：US13164448

申请日：2011-06-20

Applicant: Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US09125333B2

公开(公告)日：2015-09-01

申请号：US13183870

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC: H05K1/03 ,  H05K1/09 ,  H05K3/40

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.

Abstract translation: 用于电气应用的阻隔层。 在一些实施例中，阻挡层是层压阻挡层。 在一些实施例中，阻挡层包括梯度阻挡层。

公开(公告)号：US20130122747A1

公开(公告)日：2013-05-16

申请号：US13296785

申请日：2011-11-15

Applicant: Cyprian Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01R24/28

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.

Abstract translation: 互连部件包括具有开口的元件，延伸穿过开口彼此电绝缘的多个导体以及彼此电绝缘的多个第二触点。 该元件由热膨胀系数小于10ppm /℃的材料构成。 至少一些导体沿开口的至少一个内表面延伸。 导体在第一表面限定多个可润湿的第一接触。 第一触点在厚度方向上与开口至少部分地对齐，并且彼此电绝缘。

公开(公告)号：US20130014979A1

公开(公告)日：2013-01-17

申请号：US13183920

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Craig Mitchell

IPC: H05K1/09 ,  H05K3/10 ,  H05K1/00

CPC classification number: H01R13/03 ,  H05K1/09 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/09745 ,  Y10T29/49155

Abstract: Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use.

Abstract translation: 电触头包括其中具有多个空腔的表面及其制造和使用方法。