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    DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE
    4.
    发明申请
    DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE 有权
    集成电路或基板上器件的芯片屏蔽结构设计结构

    公开(公告)号：US20090055790A1

    公开(公告)日：2009-02-26

    申请号：US12046750

    申请日：2008-03-12

    申请人： Hanyi DING ,  Kai D. FENG ,  Zhong-Xiang HE ,  Xuefeng LIU

    发明人： Hanyi DING ,  Kai D. FENG ,  Zhong-Xiang HE ,  Xuefeng LIU

    IPC分类号： G06F17/50

    CPC分类号： G01R1/18 ,  G01R31/2851 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

    摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置 分别。 该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

    STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME 有权
    高Q值电感器的结构与设计结构及其制造方法

    公开(公告)号：US20120267794A1

    公开(公告)日：2012-10-25

    申请号：US13535412

    申请日：2012-06-28

    申请人： Hanyi DING ,  Mete ERTURK ,  Robert A. GROVES ,  Zhong-Xiang HE ,  Peter J. LINDGREN ,  Anthony K. STAMPER

    发明人： Hanyi DING ,  Mete ERTURK ,  Robert A. GROVES ,  Zhong-Xiang HE ,  Peter J. LINDGREN ,  Anthony K. STAMPER

    IPC分类号： H01L23/48

    CPC分类号： H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

    摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

    PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
    8.
    发明申请
    PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK 有权
    单层和多层金属绝缘子 - 金属整合与单面蒙皮的工艺

    公开(公告)号：US20120184081A1

    公开(公告)日：2012-07-19

    申请号：US13432440

    申请日：2012-03-28

    申请人： Anil K. CHINTHAKINDI ,  Douglas D. COOLBAUGH ,  Keith E. DOWNES ,  Ebenezer E. ESHUN ,  Zhong-Xiang HE ,  Robert M. RASSEL ,  Anthony K. STAMPER

    发明人： Anil K. CHINTHAKINDI ,  Douglas D. COOLBAUGH ,  Keith E. DOWNES ,  Ebenezer E. ESHUN ,  Zhong-Xiang HE ,  Robert M. RASSEL ,  Anthony K. STAMPER

    IPC分类号： H01L21/02

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 提供一种制造MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。