公开(公告)号：US20100314779A1

公开(公告)日：2010-12-16

申请号：US12787873

申请日：2010-05-26

申请人： Hiromasa TAKEDA ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

发明人： Hiromasa TAKEDA ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

IPC分类号： H01L23/485

CPC分类号： H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row.

摘要翻译： 半导体器件包括第一焊盘行和第二焊盘行，第一接地电位供应电极，连接到设置在第一焊盘行附近的第一互连件，以及第二接地电位供应电极，其连接到靠近 第二垫排。 第一焊盘行包括连接到芯片内的第一电路并经由第一接合线连接到第一互连的第一焊盘，并且包括连接到芯片内的第二电路并经由第二焊盘连接到第二互连的第二焊盘 接合线穿过第二垫排。

公开(公告)号：US20110084395A1

公开(公告)日：2011-04-14

申请号：US12923712

申请日：2010-10-05

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yu Hasegawa

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yu Hasegawa

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality.

摘要翻译： 半导体器件包括其上安装半导体芯片的半导体芯片和封装衬底。 封装衬底具有连接到半导体芯片的内部端子，连接到内部端子的前表面布线，连接到外部电极的后表面布线以及连接前表面布线和背面布线的触点。 在多个接触中，用于信号传输的布线中包括的一些触点设置在内部端子附近。 因此，从半导体芯片引出的信号立即从封装基板的芯片安装表面取走。 这降低了封装衬底和芯片之间的布线之间的浮动电容，从而提高了信号质量。

公开(公告)号：US08569898B2

公开(公告)日：2013-10-29

申请号：US12776070

申请日：2010-05-07

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Dai Sasaki

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Dai Sasaki

IPC分类号： H01L23/498

CPC分类号： H01L24/85 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2224/49171 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599

摘要： Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.

摘要翻译： 提供一种半导体器件，其具有安装在小型封装基板上的半导体芯片，小型封装基板包括槽，大量的外部连接端子和结合指状物。 接合指状物连接到外部连接端子。 接合手指构成沿着槽的每个较长侧的中心部分和接合手指区域的端部部分的接合手指装置。 该装置包括位于距槽的每个较长侧较近的距离处的第一粘结手指阵列和位于比第一粘结手指阵列距每个较长边的距离更远的距离的第二阵列 插槽。 接合手指区域的中心部分包​​括第二接合手指阵列，并且接合指区域的端部部分包括第一接合手指阵列。

公开(公告)号：US08426983B2

公开(公告)日：2013-04-23

申请号：US13014235

申请日：2011-01-26

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri

IPC分类号： H01L23/48

CPC分类号： H01L24/49 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

摘要翻译： 半导体器件可以包括：经由间隙彼此分离的第一和第二布线板; 半导体芯片; 第一组和第二组电极垫; 以及第一组和第二组连接垫。 半导体芯片固定在第一和第二布线板的上表面上，并且具有与间隙相邻的第一部分。 第一和第二组电极焊盘设置在第一部分上。 第一和第二组电极焊盘分别与第一和第二布线板的侧表面相对准。 第一和第二布线板的侧表面彼此面对。 第一和第二组连接焊盘分别设置在第一和第二布线板的下表面上。 第一和第二组连接焊盘分别与第一和第二布线板的侧表面相对准。

公开(公告)号：US20110063936A1

公开(公告)日：2011-03-17

申请号：US12881786

申请日：2010-09-14

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

IPC分类号： G11C7/06

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C11/409 ,  G11C2207/105

摘要： A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad for sense amplifier ground potential among plural electrode pads included in a pad row. The second conductive line extends to the opposite side of the first conductive line with the pad row as a reference.

摘要翻译： 半导体器件包括用于读出放大器接地电位的焊盘作为向读出放大器提供接地电位电压的电极焊盘，连接到用于读出放大器接地电位的焊盘的第一导线以及连接到最靠近 用于读出放大器的焊盘用于焊盘行中包括的多个电极焊盘之间的接地电位。 第二导电线延伸到第一导电线的相对侧，焊盘排作为参考。

公开(公告)号：US20100289141A1

公开(公告)日：2010-11-18

申请号：US12776070

申请日：2010-05-07

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Dai Sasaki

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Dai Sasaki

IPC分类号： H01L23/498

CPC分类号： H01L24/85 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2224/49171 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599

摘要： Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that has a large number of external connection terminals. The package substrate includes a slot, the external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The bonding finger arrangement includes a first bonding finger array, which is located at a close distance from the each longer side of the slot, and a second bonding finger array, which is located at a distance farther than the distance of the first bonding finger array from the each longer side of the slot. The central section of the bonding finger area includes at least the second bonding finger array, and the end sections of the bonding finger area includes the first bonding finger array.

摘要翻译： 提供一种具有安装在具有大量外部连接端子的小尺寸封装基板上的半导体芯片的半导体器件。 封装基板包括槽，外部连接端子和接合指。 接合指状物连接到外部连接端子。 接合手指构成沿着槽的每个较长侧的中心部分和接合手指区域的端部部分的接合手指装置。 接合手指装置包括位于距离槽的每个较长侧较近的距离处的第一粘结手指阵列和位于比第一粘结手指阵列的距离更远的距离处的第二粘结手指阵列 从插槽的每个更长的一边。 接合手指区域的中心部分至少包括第二结合手指阵列，并且键合区域的端部部分包括第一粘结手指阵列。

公开(公告)号：US08587097B2

公开(公告)日：2013-11-19

申请号：US12787873

申请日：2010-05-26

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

IPC分类号： H01L27/118 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row.

摘要翻译： 半导体器件包括第一焊盘行和第二焊盘行，第一接地电位供应电极，连接到设置在第一焊盘行附近的第一互连件，以及第二接地电位供应电极，其连接到靠近 第二垫排。 第一焊盘行包括连接到芯片内的第一电路并经由第一接合线连接到第一互连的第一焊盘，并且包括连接到芯片内的第二电路并经由第二焊盘连接到第二互连的第二焊盘 接合线穿过第二垫排。

公开(公告)号：US08331182B2

公开(公告)日：2012-12-11

申请号：US12881786

申请日：2010-09-14

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Shotaro Kobayashi ,  Mitsuaki Katagiri

IPC分类号： G11C7/06

CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C11/409 ,  G11C2207/105

摘要： A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad for sense amplifier ground potential among plural electrode pads included in a pad row. The second conductive line extends to the opposite side of the first conductive line with the pad row as a reference.

摘要翻译： 半导体器件包括用于读出放大器接地电位的焊盘作为向读出放大器提供接地电位电压的电极焊盘，连接到用于读出放大器接地电位的焊盘的第一导线以及连接到最靠近 用于读出放大器的焊盘用于焊盘行中包括的多个电极焊盘之间的接地电位。 第二导电线延伸到第一导电线的相对侧，焊盘排作为参考。

公开(公告)号：US20160027754A1

公开(公告)日：2016-01-28

申请号：US14773817

申请日：2014-03-10

申请人： Mitsuaki KATAGIRI ,  Yu HASEGAWA ,  Satoshi ISA ,  PS4 Luxco S.a.r.l.

发明人： Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L22/32 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/025 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/10734 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

摘要： To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes.[Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120a, 120b) disposed on the main surface thereof; insulating films (310, 330) that cover the main surface of the semiconductor chip (100); a rewiring layer (320) that is disposed between the insulating films (310, 330); and a plurality of external terminals (340) disposed on the top of the insulating film (330). The plane size of the first pad electrode (120a) and the second pad electrode (120b) differ from one another, and the first pad electrode (120a) and the second pad electrode (120b) are connected to any of the plurality of external terminals (340) via the rewiring layer (320). According to the present invention, because the pad electrodes (120a, 120b) of different sizes are intermixed, probing can be easily performed while reducing the area occupied by the pad electrodes.

摘要翻译： 提供具有晶片级封装结构的半导体器件，其允许在减小焊盘电极占据的面积的同时进行探测。 [解决方案]在本发明中，提供了一种半导体芯片（100），其具有设置在其主表面上的第一和第二焊盘电极（120a，120b） 覆盖半导体芯片（100）的主表面的绝缘膜（310,330）; 布置在所述绝缘膜（310,330）之间的再布线层（320）; 以及设置在绝缘膜（330）的顶部上的多个外部端子（340）。 第一焊盘电极（120a）和第二焊盘电极（120b）的平面尺寸彼此不同，并且第一焊盘电极（120a）和第二焊盘电极（120b）连接到多个外部端子 （340）经由重新布线层（320）。 根据本发明，由于不同尺寸的焊盘电极（120a，120b）是混合的，所以可以容易地进行探测，同时减少焊盘电极占据的面积。

公开(公告)号：US08581417B2

公开(公告)日：2013-11-12

申请号：US12687311

申请日：2010-01-14

申请人： Yu Hasegawa ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Ken Iwakura ,  Dai Sasaki

发明人： Yu Hasegawa ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Ken Iwakura ,  Dai Sasaki

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85007 ,  H01L2224/85051 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48132 ,  H01L2924/00012 ,  H01L2924/20757 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.