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29 条记录 (耗时 0.026 秒)

    POGO pin and test socket including the same
    2.
    发明申请
    POGO pin and test socket including the same 有权
    POGO引脚和测试插座包括相同

    公开(公告)号：US20060145719A1

    公开(公告)日：2006-07-06

    申请号：US11325145

    申请日：2006-01-03

    申请人： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

    发明人： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R1/06722

    摘要： A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

    摘要翻译： 一个POGO引脚，可以测量低频产品以及RF产品，并且具有较长的使用寿命，并提供包含POGO引脚的测试插座。 POGO针包括由导电金属形成的金属柱塞，以与半导体封装件电接触;以及橡胶触针，与金属柱塞连接并由导电橡胶形成，以便电接触测试板。

    POGO pin and test socket including the same
    3.
    发明授权
    POGO pin and test socket including the same 有权
    POGO引脚和测试插座包括相同

    公开(公告)号：US07245138B2

    公开(公告)日：2007-07-17

    申请号：US11325145

    申请日：2006-01-03

    申请人： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

    发明人： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R1/06722

    摘要： A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

    摘要翻译： 一个POGO引脚，可以测量低频产品以及RF产品，并且具有较长的使用寿命，并提供包含POGO引脚的测试插座。 POGO针包括由导电金属形成的金属柱塞，以与半导体封装件电接触;以及橡胶触针，与金属柱塞连接并由导电橡胶形成，以便电接触测试板。

    Package stack and manufacturing method thereof
    4.
    发明授权
    Package stack and manufacturing method thereof 有权
    封装堆栈及其制造方法

    公开(公告)号：US07420814B2

    公开(公告)日：2008-09-02

    申请号：US11100525

    申请日：2005-04-07

    申请人： Jae-Hong Kim ,  Heui-Seog Kim ,  Wha-Su Sin ,  Jong-Keun Jeon

    发明人： Jae-Hong Kim ,  Heui-Seog Kim ,  Wha-Su Sin ,  Jong-Keun Jeon

    IPC分类号： H05K1/14

    CPC分类号： H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511

    摘要： A package stack may include a first package and a second package. The first package may have an IC chip with an active surface and a back surface. The active surface may be connected to a first major surface of a first circuit substrate. The second package may include a second IC chip with an active surface and a back surface. The back surface of the second IC chip may be attached to a first major surface of a second circuit substrate and the active surface of the second IC chip may be electrically connected to the first major surface of the second circuit substrate. The first package may be stacked on the second package so that the active surface of the second package may be electrically connected to a second major surface of the first circuit substrate of the first package. A method may involve providing a first package having a first IC chip and a first circuit substrate and providing a second package having a second IC chip and a second circuit substrate. The first and the second packages may be stacked so that the active surface of the second IC may face and be electrically connected to a major surface of the first circuit substrate.

    摘要翻译： 包装堆叠可以包括第一包装和第二包装。 第一封装可以具有带有活性表面和背面的IC芯片。 有源表面可以连接到第一电路基板的第一主表面。 第二封装可以包括具有有源表面和后表面的第二IC芯片。 第二IC芯片的背面可以附接到第二电路基板的第一主表面，并且第二IC芯片的有源表面可以电连接到第二电路基板的第一主表面。 第一封装可以堆叠在第二封装上，使得第二封装的有源表面可以电连接到第一封装的第一电路基板的第二主表面。 一种方法可以包括提供具有第一IC芯片和第一电路基板的第一封装，并提供具有第二IC芯片和第二电路基板的第二封装。 可以堆叠第一和第二封装，使得第二IC的有源表面可以面对并且电连接到第一电路基板的主表面。

    Method of processing a semiconductor wafer for manufacture of semiconductor device
    8.
    发明授权
    Method of processing a semiconductor wafer for manufacture of semiconductor device 失效
    用于制造半导体器件的半导体晶片的处理方法

    公开(公告)号：US07452753B2

    公开(公告)日：2008-11-18

    申请号：US11172689

    申请日：2005-06-30

    申请人： Dae-Sang Chun ,  Jae-Hong Kim ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Wha-Su Sin

    发明人： Dae-Sang Chun ,  Jae-Hong Kim ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Wha-Su Sin

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368

    摘要： A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.

    摘要翻译： 一种处理具有与第一表面相对的第一表面和第二表面的半导体晶片的方法。 该方法包括在其上形成有电路图案的第二表面上形成预定深度的凹槽，将保护带的第一表面附接到其上形成有凹槽的第二表面，将载带附着到保护层的第二表面上 带，使得半导体晶片的第一表面可以向上取向，将半导体晶片的第一表面除去预定的厚度，并通过凹槽将半导体晶片分成芯片，并将每个 在芯片的第一表面朝向上方的状态下的芯片接合器。 只需要一种管芯焊接机。 不需要UV型胶带。

    Semiconductor device and method of manufacturing the same
    9.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20080111235A1

    公开(公告)日：2008-05-15

    申请号：US11978370

    申请日：2007-10-29

    申请人： Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

    发明人： Hyo-Jae Bang ,  Heui-Seog Kim ,  Dong-Chun Lee ,  Seong-Chan Han ,  Jung-Hyeon Kim

    IPC分类号： H01L23/488 ,  H01L21/60

    CPC分类号： H05K3/303 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2201/2036 ,  Y02P70/613

    摘要： A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

    摘要翻译： 半导体器件包括半导体封装，电路板和间隔保持元件。 半导体封装具有从主体突出的主体和引线。 电路板具有与引线电连接的第一焊盘。 间隔保持构件插入在电路板和主体之间。 间隔保持构件保持引线与第一焊盘之间的间隔。 因此，均匀地保持引线和焊盘之间的间隔，从而提高了半导体器件的热和/或机械可靠性。

    Insert block with pusher to push semiconductor device under test
    10.
    发明授权
    Insert block with pusher to push semiconductor device under test 有权
    带推动器的插入块推动被测半导体器件

    公开(公告)号：US07151368B2

    公开(公告)日：2006-12-19

    申请号：US11243458

    申请日：2005-10-03

    申请人： Hyeck-Jin Joung ,  Heui-Seog Kim ,  Seok-Young Yoon ,  Jong-Keun Jeon

    发明人： Hyeck-Jin Joung ,  Heui-Seog Kim ,  Seok-Young Yoon ,  Jong-Keun Jeon

    IPC分类号： H01R13/62 ,  H01R13/15

    CPC分类号： G01R1/0408 ,  G01R1/0466 ,  G01R1/0483

    摘要： The present invention relates to an insert block for testing semiconductor devices. The insert block comprises one or more pushers, installed in a block body having a loading space to accommodate a semiconductor device under test, including a first push rod to apply force to one of adjacent sides of the semiconductor device under test and a second push rod to apply force to the other thereof.Accordingly, firm centering of semiconductor devices under test relative to the contact pins of the test socket along the two perpendicular axes (for instance, x and y axes) on the top or bottom surface of the semiconductor device is achieved and leads to the proper interfaces between the external terminals of the semiconductor device under test and the contact pins of the test socket, and thereby improves the quality of connection therebetween.

    摘要翻译： 本发明涉及一种用于测试半导体器件的插入块。 插入块包括一个或多个推动器，其安装在具有装载空间以容纳被测半导体器件的块体中，包括第一推杆，以对被测半导体器件的相邻侧之一施加力;第二推杆 向另一方施加力量。 因此，实现半导体器件的顶部或底部表面上沿着两个垂直轴（例如x和y轴）测试的半导体器件相对于测试插座的接触针的牢固定心，并且导致适当的接口 在被测半导体器件的外部端子和测试插座的接触引脚之间，从而提高其间的连接质量。