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    TECHNOLOGIES FOR PROCESSING NETWORK PACKETS BY AN INTELLIGENT NETWORK INTERFACE CONTROLLER
    1.
    发明申请
    TECHNOLOGIES FOR PROCESSING NETWORK PACKETS BY AN INTELLIGENT NETWORK INTERFACE CONTROLLER 审中-公开

    公开(公告)号：US20180152540A1

    公开(公告)日：2018-05-31

    申请号：US15721815

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Jose Niell ,  Brad Burres ,  Erik McShane ,  Naru Sundar ,  Alain Gravel

    IPC: H04L29/08 ,  H04L12/24 ,  H04L12/933

    Abstract: Technologies for processing network packets by a network interface controller (NIC) of a computing device include a network interface, a packet processor, and a controller device of the NIC, each communicatively coupled to a memory fabric of the NIC. The packet processor is configured to receive an event message from the memory fabric and transmit a message to the controller device, wherein the message indicates the network packet has been received and includes the memory fabric location pointer. The controller device is configured to fetch at least a portion of the received network packet from the memory fabric, write an inbound descriptor usable by one or more on-die cores of the NIC to perform an operation on the fetched portion, and restructure the network packet as a function of an outbound descriptor written by the on-die cores subsequent to performing the operation. Other embodiments are described herein.

    TECHNOLOGIES FOR PROCESSING NETWORK PACKETS IN AGENT-MESH ARCHITECTURES
    3.
    发明申请
    TECHNOLOGIES FOR PROCESSING NETWORK PACKETS IN AGENT-MESH ARCHITECTURES 审中-公开

    公开(公告)号：US20180152383A1

    公开(公告)日：2018-05-31

    申请号：US15720390

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Brad Burres ,  Ronen Chayat ,  Alain Gravel ,  Robert Hathaway ,  Amit Y. Kumar ,  Jose Niell ,  Nadav Turbovich

    IPC: H04L12/813 ,  H04L12/851 ,  H04L12/26

    Abstract: Technologies for processing network packets in an agent-mesh architecture include a network interface controller (NIC) of a computing device configured to write, by a network fabric interface of a memory fabric of the NIC, a received network packet to the memory fabric in a distributed fashion. The network fabric interface is configured to send an event message indicating the received network packet to a packet processor communicatively coupled to the memory fabric. The packet processor is configured to read, in response to having received the generated event message, at least a portion of the received network packet from the memory fabric, identify an agent of the NIC for additional processing of the received network packet, generate a network packet received event message indicating the received network packet is available for processing, and transmit the network packet received event message to the identified agent. Other embodiments are described herein.

    Technologies for flexible I/O endpoint acceleration
    7.
    发明授权
    Technologies for flexible I/O endpoint acceleration 有权

    公开(公告)号：US10783100B2

    公开(公告)日：2020-09-22

    申请号：US16366504

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： Matthew J. Adiletta ,  Brad Burres ,  Duane Galbi ,  Amit Kumar ,  Yadong Li ,  Salma Mirza ,  Jose Niell ,  Thomas E. Willis ,  William Duggan

    IPC: G06F13/20 ,  G06F13/42

    Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.

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