公开(公告)号：US20170141020A1

公开(公告)日：2017-05-18

申请号：US15086899

申请日：2016-03-31

Applicant: Invensas Corporation

Inventor： Grant Villavicencio ,  Sangil Lee ,  Roseann Alatorre ,  Javier A. Delacruz ,  Scott McGrath

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/56 ,  H01L23/053 ,  H01L21/48 ,  H01L23/31 ,  H01L23/043

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/043 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

公开(公告)号：US09508689B2

公开(公告)日：2016-11-29

申请号：US14871185

申请日：2015-09-30

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

公开(公告)号：US10806036B2

公开(公告)日：2020-10-13

申请号：US15875842

申请日：2018-01-19

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Grant Villavicencio ,  Wael Zohni

IPC: H05K3/28 ,  H05K3/10 ,  H05K1/02 ,  H05K3/00 ,  B29C45/14 ,  H01L21/56 ,  B29L31/34

Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.

公开(公告)号：US09659848B1

公开(公告)日：2017-05-23

申请号：US15086899

申请日：2016-03-31

Applicant: Invensas Corporation

Inventor： Grant Villavicencio ,  Sangil Lee ,  Roseann Alatorre ,  Javier A. Delacruz ,  Scott McGrath

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/495 ,  H01L23/043 ,  H01L23/053 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/043 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

公开(公告)号：US20160027761A1

公开(公告)日：2016-01-28

申请号：US14871185

申请日：2015-09-30

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC: H01L25/065 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract translation: 在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。 而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。 而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

公开(公告)号：US20180146557A1

公开(公告)日：2018-05-24

申请号：US15875842

申请日：2018-01-19

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Grant Villavicencio ,  Wael Zohni

IPC: H05K3/10 ,  B29C45/14 ,  H05K1/02 ,  H05K3/00 ,  B29L31/34

CPC classification number: H05K3/103 ,  B29C45/14065 ,  B29C45/14221 ,  B29C45/14655 ,  B29C45/14754 ,  B29C2045/1477 ,  B29L2031/3425 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0296 ,  H05K3/0014 ,  H05K2201/10757 ,  H05K2201/10818 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.

公开(公告)号：US09888579B2

公开(公告)日：2018-02-06

申请号：US14639789

申请日：2015-03-05

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Grant Villavicencio ,  Wael Zohni

IPC: H05K3/10 ,  H05K1/02 ,  H05K3/00 ,  B29C45/14 ,  B29L31/34

CPC classification number: H05K3/103 ,  B29C45/14065 ,  B29C45/14221 ,  B29C45/14655 ,  B29C45/14754 ,  B29C2045/1477 ,  B29L2031/3425 ,  H01L21/566 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0296 ,  H05K3/0014 ,  H05K2201/10757 ,  H05K2201/10818 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.

公开(公告)号：US20150056753A1

公开(公告)日：2015-02-26

申请号：US14480373

申请日：2014-09-08

Applicant: Invensas Corporation

Inventor： Keith Lake Barrie ,  Suzette K. Pangrle ,  Grant Villavicencio ,  Jeffrey S. Leal

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L23/293 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/038 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/1131 ,  H01L2224/11848 ,  H01L2224/13017 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13347 ,  H01L2224/16145 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/24992 ,  H01L2224/24997 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/831 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to “bleed” laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

Abstract translation: 裸片在互连端附近在互连边缘附近具有互连焊盘，并且互连面的至少一部分由保形电介质涂层覆盖，其中在电介质涂层上的互连迹线与电介质的表面形成高界面角 涂层。 由于迹线具有较高的界面角度，因此互连材料横向“渗出”的趋势得到缓解，避免了相邻迹线的接触或重叠。 互连迹线包括可固化的导电互连材料; 也就是说，它包括可以以可流动形式施加的材料，然后固化或允许其固化以形成导电迹线。 此外，一种方法包括在形成迹线之前，用CF 4等离子体处理对保形电介质涂层的表面进行处理。