公开(公告)号：US09825002B2

公开(公告)日：2017-11-21

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

公开(公告)号：US20170141020A1

公开(公告)日：2017-05-18

申请号：US15086899

申请日：2016-03-31

Applicant: Invensas Corporation

Inventor： Grant Villavicencio ,  Sangil Lee ,  Roseann Alatorre ,  Javier A. Delacruz ,  Scott McGrath

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/56 ,  H01L23/053 ,  H01L21/48 ,  H01L23/31 ,  H01L23/043

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/043 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2224/81805 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15333 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

公开(公告)号：US20130119117A1

公开(公告)日：2013-05-16

申请号：US13667289

申请日：2012-11-02

Applicant: Invensas Corporation

Inventor： Scott McGrath

IPC: H01L23/00

CPC classification number: H01L24/43 ,  B23K20/004 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/1134 ,  H01L2224/29099 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/078 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/05552

Abstract: A bonding wedge particularly suitable for making wire off-die interconnects includes an aperture opening onto a notch or pocket adjacent to the rear of a foot. The foot includes a heel portion and a toe portion. When the bonding wedge is in use, a wire is fed from feedstock through the aperture and the notch or pocket, and passes beneath the foot and extends beyond the toe. The toe is configured to mitigate upward displacement of the free end of the wire during the bonding process.

Abstract translation: 特别适用于制造线离线互连的接合楔包括邻近脚后缘的凹口或口袋上的孔口。 足部包括脚跟部分和脚趾部分。 当使用结合楔时，电线通过孔和凹口或口袋从原料进料，并且在脚下方延伸并延伸超过脚趾。 脚趾构造成在接合过程中减轻线的自由端的向上位移。

公开(公告)号：US20170040270A1

公开(公告)日：2017-02-09

申请号：US14819744

申请日：2015-08-06

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Bongsub Lee ,  Scott McGrath ,  Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Akash Agrawal

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L24/03 ,  H01L21/31144 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/03009 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/10126 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.

Abstract translation: 处理互连元件的方法可以包括提供具有前后相对表面和导电结构的衬底元件，覆盖前表面的第一电介质层和在第一介电层的第一表面处的多个导电触点，以及 第二电介质层覆盖在后表面上并且在第二介电层的第二表面处具有导电元件。 该方法还可以包括去除第二电介质层的一部分以减小该部分的厚度，并且提供具有第一厚度的第二介电层的凸起部分和具有第二厚度的下降部分。 第一厚度可以大于第二厚度。 导电元件的至少一部分可以凹陷到第二介电层的第一厚度的高度以下。

公开(公告)号：US20170018529A1

公开(公告)日：2017-01-19

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

Abstract translation: 微电子组件包括堆叠的半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 芯片端子可以沿着朝向相应芯片的边缘表​​面的方向从每个芯片的前表面处的触点延伸。 芯片堆叠以一定角度安装到基板，使得芯片的边缘表​​面面向基板的主表面，该主表面限定横向于即不平行于多个平行平面的第二平面。 导电材料将芯片端子与相应的衬底触点电连接。

公开(公告)号：US09252116B2

公开(公告)日：2016-02-02

申请号：US14242206

申请日：2014-04-01

Applicant: Invensas Corporation

Inventor： Scott Jay Crane ,  Simon J. S. McElrea ,  Scott McGrath ,  Weiping Pan ,  De Ann Eileen Melcher ,  Marc E. Robinson

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/29

CPC classification number: H01L24/83 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/27452 ,  H01L2224/29005 ,  H01L2224/29006 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

Abstract translation: 半导体管芯上的保形涂层提供了管芯和支撑件之间的粘附。 不需要额外的粘合剂将模具固定在支撑件上。 共形涂层在组装期间保护模具，并且用于使模具与模具可接触的导电部件电绝缘。 保形涂层可以是有机聚合物，例如聚对二甲苯。 此外，将模具粘附到可任选地是另一个模具的支撑件上的方法包括在模具和支撑件之间提供共形的涂层，以及加热模具和支撑件之间的涂层。 保形涂层可以设置在模具的表面的芯片附着区域上，或在支撑体的表面的模具安装区域上，或者在模具的表面的芯片附着区域上以及模具安装区域 的支撑体的表面; 并且可以在将模具放置在支撑件上之后提供保形涂层。

公开(公告)号：US20160027761A1

公开(公告)日：2016-01-28

申请号：US14871185

申请日：2015-09-30

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC: H01L25/065 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract translation: 在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。 而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。 而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

公开(公告)号：US09824999B2

公开(公告)日：2017-11-21

申请号：US14969779

申请日：2015-12-15

Applicant: Invensas Corporation

Inventor： Scott Jay Crane ,  Simon J. S. McElrea ,  Scott McGrath ,  Weiping Pan ,  De Ann Eileen Melcher ,  Marc E. Robinson

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/29

CPC classification number: H01L24/83 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/27452 ,  H01L2224/29005 ,  H01L2224/29006 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

公开(公告)号：US09508689B2

公开(公告)日：2016-11-29

申请号：US14871185

申请日：2015-09-30

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

公开(公告)号：US09859234B2

公开(公告)日：2018-01-02

申请号：US14819744

申请日：2015-08-06

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Bongsub Lee ,  Scott McGrath ,  Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Akash Agrawal

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/532

CPC classification number: H01L24/03 ,  H01L21/31144 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/03009 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/10126 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.