公开(公告)号：US20130087916A1

公开(公告)日：2013-04-11

申请号：US13270850

申请日：2011-10-11

申请人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L21/50

CPC分类号： H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

公开(公告)号：US09117682B2

公开(公告)日：2015-08-25

申请号：US13270850

申请日：2011-10-11

申请人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC分类号： H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

摘要： Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

摘要翻译： 公开了封装半导体器件的方法及其结构。 在一个实施例中，一种封装半导体器件的方法包括提供载体晶片，提供多个管芯，以及在载体晶片上形成管芯洞穴材料。 在模具洞穴材料中形成多个模具洞穴。 将多个模具中的至少一个放置在模具洞穴材料中的多个模具洞穴的每一个中。 形成多个封装，所述多个封装中的每个封装形成在所述多个管芯中的相应的至少一个管芯上。

公开(公告)号：US09000584B2

公开(公告)日：2015-04-07

申请号：US13338820

申请日：2011-12-28

申请人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Nai-Wei Liu ,  Yi-Chao Mao ,  Wan-Ting Shih ,  Tsan-Hua Tung

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Nai-Wei Liu ,  Yi-Chao Mao ,  Wan-Ting Shih ,  Tsan-Hua Tung

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

摘要： The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

摘要翻译： 提供了在半导体器件基板上形成模制化合物以使得晶片级封装（WLP）中的扇出结构能够实现的机制。 这些机构涉及覆盖围绕接触垫的绝缘层的表面的部分。 这些机制提高了包装的可靠性和包装过程的过程控制。 这些机理还降低了界面分层的风险，并且在后续处理过程中绝缘层过度消除气泡。 这些机制进一步改善了平面化终点。 通过利用接触焊盘和绝缘层之间的保护层，可以减少铜外扩散，并且还可以提高接触焊盘和绝缘层之间的粘附。

公开(公告)号：US09691706B2

公开(公告)日：2017-06-27

申请号：US13452140

申请日：2012-04-20

申请人： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

发明人： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC分类号： H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31

CPC分类号： H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

摘要： A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

公开(公告)号：US09662812B2

公开(公告)日：2017-05-30

申请号：US13485307

申请日：2012-05-31

申请人： Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

发明人： Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC分类号： B29C43/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81

摘要： A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

公开(公告)号：US08772929B2

公开(公告)日：2014-07-08

申请号：US13297992

申请日：2011-11-16

申请人： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

发明人： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L21/78

CPC分类号： H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

摘要： A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

摘要翻译： 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。

公开(公告)号：US08703542B2

公开(公告)日：2014-04-22

申请号：US13539229

申请日：2012-06-29

申请人： Jing-Cheng Lin ,  Jui-Pin Hung

发明人： Jing-Cheng Lin ,  Jui-Pin Hung

IPC分类号： H01L21/50

CPC分类号： H01L24/10 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/82001 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00

摘要： The embodiments of mechanisms of wafer-level packaging (WLP) described above utilize a planarization stop layer to determine an end-point of the removal of excess molding compound prior to formation of redistribution lines (RDLs). Such mechanisms of WLP are used to implement fan-out and multi-chip packaging. The mechanisms are also usable to manufacture a package including chips (or dies) with different types of external connections. For example, a die with pre-formed bumps can be packaged with a die without pre-formed bumps.

摘要翻译： 上述晶片级封装（WLP）的机理的实施例利用平坦化停止层来确定形成再分配线（RDL）之前除去过量模塑料的终点。 WLP的这种机制被用于实现扇出和多芯片封装。 这些机构还可用于制造包括具有不同类型的外部连接的芯片（或模具）的包装。 例如，具有预先形成的凸块的模具可以与模具封装而没有预先形成的凸块。

公开(公告)号：US20130119552A1

公开(公告)日：2013-05-16

申请号：US13298126

申请日：2011-11-16

申请人： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

摘要： A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

摘要翻译： 一种器件包括底部芯片和结合到底部芯片的有源顶部管芯。 虚设裸片连接到底部芯片。 虚设裸片与底部芯片电绝缘。

公开(公告)号：US20130115854A1

公开(公告)日：2013-05-09

申请号：US13290879

申请日：2011-11-07

申请人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B24B49/10

CPC分类号： H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

摘要翻译： 执行磨削的方法包括：选择用于晶片研磨工艺的目标轮加载，以及对晶片进行研磨处理。 随着研磨过程的进行，测量研磨过程的轮载荷。 在达到目标轮加载后停止研磨过程。 该方法或者包括选择晶片研磨过程的目标反射率，以及对晶片进行研磨处理。 随着研磨过程的进行，测量从晶片表面反射的光的反射率。 在一个反射率达到目标反射率之后停止研磨过程。

公开(公告)号：US09679783B2

公开(公告)日：2017-06-13

申请号：US13208197

申请日：2011-08-11

申请人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.