公开(公告)号：US20030021549A1

公开(公告)日：2003-01-30

申请号：US09911472

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Marc Chason ,  Daniel Gamota

IPC: G02B006/42 ,  G02B006/12

CPC classification number: G02B6/4204

Abstract: High quality epitaxial layers of monocrystalline materials can be grown layered monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Formation of a compliant substrate may include utilizing surfactant-enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The layered monocrystalline substrates allow for the fabrication of at least one optical device with an insulating material laid over it, wherein the insulating material provides an optical aperture for use with the optical device. A conductive material can be deposited within the insulating material, and an electro-rheological lens can be inserted within the insulating material aperture, while being in contact with the conductive material.

Abstract translation: 通过形成用于生长单晶层的顺应性衬底，可以生长单晶材料的高质量外延层，以生长层状单晶衬底，例如大的硅晶片。 顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 层状单晶衬底允许制造具有铺设在其上的绝缘材料的至少一个光学器件，其中绝缘材料提供用于光学器件的光学孔。 导电材料可以沉积在绝缘材料内，并且电流变透镜可以在与导电材料接触的同时插入绝缘材料孔内。

公开(公告)号：US20030015722A1

公开(公告)日：2003-01-23

申请号：US09905935

申请日：2001-07-17

Applicant: Motorola, Inc.

Inventor： Marc Chason ,  Daniel Gamota ,  Robert Lempkowski

IPC: H01L033/00

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/15 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant-enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20030132513A1

公开(公告)日：2003-07-17

申请号：US10044777

申请日：2002-01-11

Applicant: Motorola, Inc.

Inventor： Marc Chason ,  Janice Danvir ,  Jing Qi ,  Nadia Yala

IPC: H01L023/02 ,  H01L023/22 ,  H01L023/24

CPC classification number: H01L21/563 ,  H01L23/3164 ,  H01L2224/73203 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10977 ,  Y02P70/613

Abstract: An interposer-based semiconductor package (40) having at least one semiconductor die (21) attached to one side thereof also has, prior to placement on a printed wiring board (61), an underfill material (31) disposed at least partially thereon. Depending upon the embodiment, the underfill material (31) may initially cover interface electrodes (12) on the interposer (11). Such material (31) can be selectively removed to partially expose the interface electrodes (12). In other embodiments, apertures (101) can be left in the underfill material (31) during deposition, or formed after the underfill material (31) has been deposited, and the interface electrodes (12) subsequently formed in the apertures (101). Deposition of the underfill material (31) can be done with a single interposer-based package (40) or simultaneously with a plurality of such packages. Once deposited, the underfill material can be processed to render it relatively stable an substantially non-tacky. So processed, the package can be easily handled.

Abstract translation: 在其一侧附近具有至少一个半导体管芯（21）的插入件半导体封装（40）在放置在印刷电路板（61）上之前还具有至少部分设置在其上的底部填充材料（31）。 根据实施例，底部填充材料（31）可以初始地覆盖插入件（11）上的界面电极（12）。 可以选择性地去除这种材料（31）以部分地暴露界面电极（12）。 在其他实施例中，孔（101）可以在沉积期间留在底部填充材料（31）中，或者在已经沉积底部填充材料（31）之后形成，并且接口电极（12）随后形成在孔（101）中。 底部填充材料（31）的沉积可以用单个基于插入件的包装（40）或与多个这样的包装同时进行。 一旦沉积，可以处理底部填充材料使其相对稳定，基本上不粘。 这样处理，包装很容易处理。

公开(公告)号：US20030022414A1

公开(公告)日：2003-01-30

申请号：US09911627

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Keryn Lian ,  Marc Chason ,  Daniel Gamota ,  Barbara Foley Barenburg

IPC: H01L033/00

CPC classification number: H01L27/144 ,  H01L27/15 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/183 ,  H01S2301/173

Abstract: A opto-electronic semiconductor structure having an electrochromic switch includes a monocrystalline silicon substrate and an amorphous oxide material overlying the monocrystalline silicon substrate. A monocrystalline perovskite oxide material overlies the amorphous oxide material and a monocrystalline compound semiconductor material overlies the monocrystalline perovskite oxide material. An optical source component that is adapted to transmit radiant energy may be formed within the monocrystalline compound semiconductor material. An electrochromic switch may be optically coupled to the optical source component. An optical detector component that is adapted to receive radiant energy may be formed within the monocrystalline compound semiconductor material. An electrochromic switch may be optically coupled to the optical detector component.

Abstract translation: 具有电致变色开关的光电子半导体结构包括单晶硅衬底和覆盖在单晶硅衬底上的无定形氧化物材料。 单晶钙钛矿氧化物材料覆盖无定形氧化物材料，单晶化合物半导体材料覆盖在单晶钙钛矿氧化物材料上。 可以在单晶化合物半导体材料内形成适于透射辐射能的光源组件。 电致变色开关可以光耦合到光源组件。 可以在单晶化合物半导体材料内形成适于接收辐射能的光学检测器部件。 电致变色开关可以光学耦合到光学检测器部件。

公开(公告)号：US20030017690A1

公开(公告)日：2003-01-23

申请号：US09906784

申请日：2001-07-18

Applicant: MOTOROLA, INC.

Inventor： Marc Chason

IPC: C30B001/00 ,  H01L021/20 ,  H01L021/36 ,  H01L021/3205 ,  H01L021/4763 ,  H01L021/28

CPC classification number: H01L24/82 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/5389 ,  H01L27/0605 ,  H01L27/0688 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/0107 ,  H01L2924/01072 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Once the integrated circuit having the above layers is fabricated, it is attached to a circuit board. The integrated circuit has an insulative layer formed on a side edge and electrical signals are passed from the integrated circuit to an input/output pad, through a conductive path and then to another input/output pad that is located on the circuit board.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 一旦制造了具有上述层的集成电路，则其被附接到电路板。 集成电路具有形成在侧边缘上的绝缘层，并且电信号通过导电路径从集成电路传递到输入/输出焊盘，然后到达位于电路板上的另一个输入/输出焊盘。

公开(公告)号：US20030013218A1

公开(公告)日：2003-01-16

申请号：US09900883

申请日：2001-07-10

Applicant: Motorola, Inc.

Inventor： Marc Chason

IPC: H01L029/06 ,  H01L031/0328 ,  H01L021/00 ,  H01L031/0336 ,  H01L031/072 ,  H01L031/109 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L27/0688 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0262 ,  H01S5/0264 ,  H01S2301/173 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20040048445A1

公开(公告)日：2004-03-11

申请号：US10236619

申请日：2002-09-06

Applicant: Motorola, Inc.

Inventor： Marc Chason ,  Paul Brazis ,  Krishna Kalyanasundaram ,  Daniel Gamota

IPC: H01L021/76

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wafer (10) having integrated circuit elements formed therein is thinned and a first carrier (41) is adhered thereto. The first carrier (41) facilitates handling of the thinned wafer (30). A second carrier (51) is then adhered as well and the various integrated circuits are singulated to yield a plurality of thinned die (81). Once the thinned die is mounted to a desired substrate (91), the first carrier (41) is readily removed. In one embodiment, the first carrier (41) has an adhesive that becomes less adherent when exposed to a predetermined stimulus (such as a given temperature range or a given frequency range of photonic energy). Such thinned die (or modules containing such die) are readily amenable to stacking in order to achieve significantly increased circuit densities.

公开(公告)号：US20030015705A1

公开(公告)日：2003-01-23

申请号：US09905980

申请日：2001-07-17

Applicant: Motorola, Inc.

Inventor： Marc Chason ,  Daniel Gamota ,  Robert Lempkowski

IPC: H01L029/04 ,  H01L031/036

CPC classification number: H01L27/142 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L27/14 ,  H01S5/021 ,  H01S5/0261 ,  H01S5/042 ,  H01S2301/173 ,  Y02E10/50

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。

公开(公告)号：US20040232430A1

公开(公告)日：2004-11-25

申请号：US10878414

申请日：2004-06-29

Applicant: Motorola, Inc.

Inventor： Robert Lempkowski ,  Marc Chason

IPC: H01L033/00

CPC classification number: H01L21/8221 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/15 ,  H01L29/812 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/0261 ,  H01S5/183 ,  H01S2301/173 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A high quality layer of compound semiconductor material is used to form a source component and a receiver component that are interconnected with an antenna and each other within a semiconductor structure that can detect a parameter, such as the speed, of an object.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 使用高质量的化合物半导体材料层来形成源天线组件和接收器组件，该组件和接收器组件可以在半导体结构内互相连接，该半导体结构可以检测物体的诸如速度的参数。

公开(公告)号：US20040118599A1

公开(公告)日：2004-06-24

申请号：US10328326

申请日：2002-12-23

Applicant: MOTOROLA, INC.

Inventor： Marc Chason ,  Jan Danvir

IPC: H05K001/16

CPC classification number: B81C1/00333 ,  H01L21/563 ,  H01L23/48 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L31/0203 ,  H01L33/62 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention provides a method for attaching a flip chip to a printed wiring board. A bumped opto-electronic or electromechanical flip chip is provided. An underfill material is applied to a first portion of the flip chip, wherein a second portion of the flip chip is free of the underfill material. The flip chip is positioned on a printed wiring board, and a bumped portion of the flip chip is heated to electrically connect the flip chip to the printed wiring board. The second portion of the flip chip remains free of the underfill material when the flip chip is electrically connected to the printed wiring board.

Abstract translation: 本发明提供了一种将倒装芯片附接到印刷电路板的方法。 提供了一种凸起的光电或机电倒装芯片。 将底部填充材料施加到倒装芯片的第一部分，其中倒装芯片的第二部分没有底部填充材料。 倒装芯片位于印刷线路板上，并且加热倒装芯片的凸起部分以将倒装芯片电连接到印刷线路板。 当倒装芯片电连接到印刷线路板时，倒装芯片的第二部分保持没有底部填充材料。