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    Magnetic head circuit having a write current changeover circuit with a clamp voltage depending on write current for high-speed data transfer
    1.
    发明授权
    Magnetic head circuit having a write current changeover circuit with a clamp voltage depending on write current for high-speed data transfer 失效
    磁头电路具有写入电流切换电路，其具有取决于用于高速数据传输的写入电流的钳位电压

    公开(公告)号：US5392172A

    公开(公告)日：1995-02-21

    申请号：US010146

    申请日：1993-01-28

    申请人： Masaki Yoshinaga ,  Noriaki Hatanaka ,  Tomoaki Hirai ,  Yuji Nagaya ,  Tsuyoshi Hirose ,  Tadao Kaji

    发明人： Masaki Yoshinaga ,  Noriaki Hatanaka ,  Tomoaki Hirai ,  Yuji Nagaya ,  Tsuyoshi Hirose ,  Tadao Kaji

    IPC分类号： G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B5/035 ,  G11B5/40 ,  G11B5/455 ,  G11B19/04

    CPC分类号： G11B5/012 ,  G11B5/02 ,  G11B5/022 ,  G11B5/035 ,  G11B5/40 ,  G11B5/455 ,  G11B19/04 ,  G11B2005/0013

    摘要： A magnetic head circuit for a plurality of magnetic heads includes two emitter follower transistors for receiving magnetic head writing data, two differential transistors connected to the two emitter follower transistors for performing differential operation control thereover, and two resistors connected to collectors of the two differential transistors for supplying a base current to the two emitter follower transistors, and wherein the emitter follower transistors are connected in series with each other to perform differential switch operations over a magnetic head writing current. A magnetic head fly-back voltage has a clamp voltage which varies according to a writing current flowing through a pair of signal terminals. A pair of differential transistors, whose bases are connected to the pair of signal terminals and whose emitters are connected directly to each other, are operated according to a voltage appearing between the pair of signal terminals. Connected to the collectors of the pair of differential transistors are amplification transistors respectively. Connected to outputs of the amplification transistors are post-amplifiers. Such a connection configuration provides a small mirror capacitance as viewed from the bases of the amplification transistors. A high writing and reading accessing speed to the magnetic heads can be realized.

    摘要翻译： 用于多个磁头的磁头电路包括用于接收磁头写入数据的两个射极跟随器晶体管，连接到两个射极跟随器晶体管的两个差分晶体管，用于执行差分操作控制，以及连接到两个差分晶体管的集电极的两个电阻器 用于向两个射极跟随器晶体管提供基极电流，并且其中所述射极跟随器晶体管彼此串联连接以在磁头写入电流上进行差分开关操作。 磁头反向电压具有根据流过一对信号端子的写入电流而变化的钳位电压。 一对差分晶体管的基极连接到该对信号端并且其发射极彼此直接连接的差分晶体管根据出现在一对信号端子之间的电压而被操作。 连接到该对差分晶体管的集电极分别是放大晶体管。 连接到放大晶体管的输出端是后置放大器。 这种连接配置提供从放大晶体管的基极观察的小镜电容。 可以实现对磁头的高写入和读取访问速度。

    Frequency divider
    5.
    再颁专利
    Frequency divider 失效
    分频器

    公开(公告)号：USRE32605E

    公开(公告)日：1988-02-16

    申请号：US749717

    申请日：1985-06-28

    申请人： Kiichi Yamashita ,  Junichi Nakagawa ,  Tadao Kaji

    发明人： Kiichi Yamashita ,  Junichi Nakagawa ,  Tadao Kaji

    IPC分类号： H03B19/00 ,  H03K3/72 ,  H03K23/54 ,  H03K23/64 ,  H03K23/66

    CPC分类号： H03K23/667 ,  H03K23/54

    摘要： In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.

    Method of fabricating semiconductor device using at least two sorts of insulating films different from each other
    6.
    发明授权
    Method of fabricating semiconductor device using at least two sorts of insulating films different from each other 失效
    使用彼此不同的至少两种绝缘膜制造半导体器件的方法

    公开(公告)号：US3977920A

    公开(公告)日：1976-08-31

    申请号：US500067

    申请日：1974-08-23

    申请人： Ichiro Imaizumi ,  Tadao Kaji ,  Akio Hayasaka ,  Keijiro Uehara

    发明人： Ichiro Imaizumi ,  Tadao Kaji ,  Akio Hayasaka ,  Keijiro Uehara

    IPC分类号： H01L21/033 ,  H01L29/735 ,  H01L21/22

    CPC分类号： H01L21/033 ,  H01L29/735 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/106 ,  Y10S148/114 ,  Y10S148/167

    摘要： A lateral transistor or the like is made by the steps of forming a first insulating layer on a semiconductor substrate and providing a first hole in this insulating layer so as to expose a first surface portion of the substrate. An impurity of a first conductivity type is introduced through the hole and a second hole is formed in the insulating layer so as to expose a second surface portion of the substrate spaced apart from the first portion. Then, a second insulating layer of a material different from that of the first layer is formed on the first insulating layer and on the first and second surface portions of the substrate. Subsequently, third and fourth holes are formed in the second insulating layer within the confines of these holes to expose at least portions of the first and second surface portions of the substrate. Then, an impurity of a second conductivity type is introduced into the exposed first and second surface portions of the substrate through the third and fourth holes.

    摘要翻译： 横向晶体管等通过在半导体衬底上形成第一绝缘层并在该绝缘层中提供第一孔以暴露衬底的第一表面部分的步骤制成。 通过孔引入第一导电类型的杂质，并且在绝缘层中形成第二孔，以暴露基板与第一部分间隔开的第二表面部分。 然后，在第一绝缘层和基板的第一和第二表面部分上形成与第一层不同的材料的第二绝缘层。 随后，在这些孔的范围内的第二绝缘层中形成第三和第四孔，以暴露基板的第一和第二表面部分的至少一部分。 然后，通过第三孔和第四孔将第二导电类型的杂质引入到基板的暴露的第一和第二表面部分中。

    Method of fabricating semiconductor device
    7.
    发明授权
    Method of fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US4073054A

    公开(公告)日：1978-02-14

    申请号：US714197

    申请日：1976-08-13

    申请人： Tadao Kaji ,  Yoshio Homma

    发明人： Tadao Kaji ,  Yoshio Homma

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  B01J17/00

    CPC分类号： H01L21/76232 ,  H01L21/31055 ,  H01L21/31105 ,  H01L29/0642 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/118

    摘要： An improved method for forming an isolation region of electrical insulator between elements of a semiconductor device, comprising depositing an electrical insulator at a low temperature to cover one major surface of a semiconductor substrate and to fill a groove provided in this surface of the semiconductor substrate, coating the electrical insulator layer with another electrical insulator which is etched at a rate approximately equivalent to that of the former electrical insulator, so as to make the entire top surface of the electrical insulator layer parallel to the major surface of the substrate, and then applying physical etching using ions to remove the electrical insulator layers until the surface of the substrate is exposed, whereby to provide in the groove an isolation region having a satisfactory surface flatness.

    摘要翻译： 一种用于在半导体器件的元件之间形成电绝缘体的隔离区域的改进方法，包括在低温下沉积电绝缘体以覆盖半导体衬底的一个主表面并填充设置在该半导体衬底的该表面中的沟槽， 用另一个电绝缘体涂覆电绝缘层，该电绝缘体的蚀刻速度与前述电绝缘体大致相同，以便使电绝缘体层的整个顶表面平行于衬底的主表面，然后施加 使用离子的物理蚀刻去除电绝缘体层，直到基板的表面露出，从而在凹槽中提供具有令人满意的表面平坦度的隔离区域。

    Method of forming closely spaced electrodes onto semiconductor device
    9.
    发明授权
    Method of forming closely spaced electrodes onto semiconductor device 失效
    在半导体器件上形成紧密间隔的电极的方法

    公开(公告)号：US3975818A

    公开(公告)日：1976-08-24

    申请号：US483356

    申请日：1974-06-26

    申请人： Tadao Kaji ,  Takeki Katsube

    发明人： Tadao Kaji ,  Takeki Katsube

    IPC分类号： H01L21/00 ,  H01L21/285 ,  H01L21/316 ,  H01L21/60 ,  H01L23/485 ,  B01J17/00

    CPC分类号： H01L21/76897 ,  H01L21/00 ,  H01L21/28525 ,  H01L21/31604 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/018 ,  Y10S148/02 ,  Y10S148/111 ,  Y10S148/116 ,  Y10S438/901

    摘要： A method of forming at least two electrodes of a portion of a semiconductor device, the portion including one or more semiconductor regions and being covered with an insulating protective film, comprises the steps of providing a hole for the first electrode in the insulating protective film, forming the first electrode through the hole, rendering the surface of the first electrode insulative, providing a hole for the second electrode in the insulating protective film by employing the insulative surface of the first electrode as at least a part of a mask, and forming the second electrode through the second-mentioned hole, whereby the electrodes are situated in close proximity with the insulative surface of the first electrode interposed therebetween.

    摘要翻译： 一种形成半导体器件的一部分的至少两个电极的方法，包括一个或多个半导体区域并被绝缘保护膜覆盖的部分包括以下步骤：为绝缘保护膜中的第一电极提供孔， 通过该孔形成第一电极，使第一电极的表面绝缘，通过使用第一电极的绝缘表面作为掩模的至少一部分，为绝缘保护膜中的第二电极提供孔，并形成 第二电极通过第二提到的孔，由此电极位于与第一电极的绝缘表面相邻的位置。

    Frequency divider
    10.
    发明授权
    Frequency divider 失效
    分频器

    公开(公告)号：US4390960A

    公开(公告)日：1983-06-28

    申请号：US209112

    申请日：1980-11-21

    申请人： Kiichi Yamashita ,  Junichi Nakagawa ,  Tadao Kaji

    发明人： Kiichi Yamashita ,  Junichi Nakagawa ,  Tadao Kaji

    IPC分类号： H03B19/00 ,  H03K3/72 ,  H03K23/54 ,  H03K23/64 ,  H03K23/66 ,  G06F7/68 ,  H03K21/32

    CPC分类号： H03K23/667 ,  H03K23/54

    摘要： In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.

    摘要翻译： 在利用高频分频器的情况下，最大工作频率由分频器的延迟时间决定。 为了使该延迟时间最小化，提供了数字分频器，其具有由触发器构成的二进制计数器和耦合到所述计数器的输出的移位寄存器，其中移位寄存器的输出状态被强制地降低到响应的低电平 到用于改变所述计数器的分频数量的控制信号。 还提供一种电路，用于在所述计数器的第一级馈送触发器的输入端，其中OR输出由所述移位寄存器和所述计数器的输出组成。 因此，数字分频器可以以仅由所述触发器电路的触发频率限制的速度操作。