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30 条记录 (耗时 0.025 秒)

    Germanium channel silicon MOSFET
    1.
    发明授权
    Germanium channel silicon MOSFET 失效
    锗通道硅MOSFET

    公开(公告)号：US5019882A

    公开(公告)日：1991-05-28

    申请号：US351630

    申请日：1989-05-15

    申请人： Paul M. Solomon ,  Steven L. Wright

    发明人： Paul M. Solomon ,  Steven L. Wright

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/165 ,  H01L29/778

    CPC分类号： H01L29/66477 ,  H01L29/165 ,  H01L29/7782

    摘要： An alloy layer comprising germanium and silicon is grown on top of a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic, dislocation free growth. A layer of silicon is applied to the alloy layer. The initial silicon layer is from two to three times as thick as the alloy layer. Approximately the upper two-thirds of the silicon layer is oxidized, either thermally, anodically or by plasma anodization. The silicon layer that remains between the silicon dioxide and the alloy layer is kept thin enough so that a parasitic channel does not form on the interface between the silicon and the silicon dioxide. The germanium alloyed channel is thus suitably bounded by silicon crystalline structures on both of the channel layer surfaces. The barrier heights between silicon dioxide and silicon are very large thus providing good carrie confinement. A suitably applied voltage will result in a region of high mobility charge carriers at the interface between the alloy layer and the upper silicon layer.

    Enhancement and depletion mode selection layer for field effect transistor
    2.
    发明授权
    Enhancement and depletion mode selection layer for field effect transistor 失效
    场效应晶体管的增强和耗尽模式选择层

    公开(公告)号：US4616242A

    公开(公告)日：1986-10-07

    申请号：US731822

    申请日：1985-05-08

    申请人： Paul M. Solomon ,  Steven L. Wright

    发明人： Paul M. Solomon ,  Steven L. Wright

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L27/095 ,  H01L29/10 ,  H01L29/778 ,  H01L29/64 ,  H01L29/80

    CPC分类号： H01L27/0605 ,  H01L29/1029 ,  H01L29/1075 ,  H01L29/7786 ,  H01L29/7787

    摘要： A field effect transistor structure suitable for use in an array of such structures disposed on a common substrate (14) is formed with a source terminal (22), a drain (24) terminal, and a gate terminal (26) upon an upper surface of a semiconductor chip. The chip includes a first layer (18) and a second layer (20), the first layer being grown epitaxially upon the second layer. The first layer forms a part of the gate terminal and the second layer includes a charge conduction channel coupling the source region and the drain region. A pocket layer (16) is disposed in the second layer beneath the terminals of the transistor structure and is doped with either an donor dopant or an acceptor dopant for altering the electric field at the conduction channel to insert electrons or remove electrons therefrom so as to convert an operating mode from either an enhancement mode to a depletion mode or from a depletion mode to an enchancement mode. A substrate with a terminal on the backside thereof may be placed contiguous the bottom of said second layer, the back terminal being applied to a negative source of voltage for a transistor structure of n-channel format. The semiconductor material of the chip is a obtained from compounds of elements of the groups III and V of the periodic table.

    摘要翻译： 适用于布置在公共衬底（14）上的这种结构阵列中的场效应晶体管结构形成有源极端子（22），漏极（24）端子和栅极端子（26） 的半导体芯片。 芯片包括第一层（18）和第二层（20），第一层在第二层上外延生长。 第一层形成栅极端子的一部分，第二层包括耦合源极区和漏极区的电荷传导沟道。 袋状层（16）设置在晶体管结构的端子下方的第二层中，并且掺杂有施主掺杂剂或受体掺杂剂，用于改变导电沟道处的电场以插入电子或从其中去除电子，以便 将操作模式从增强模式转换为耗尽模式或从耗尽模式转换到增强模式。 在其背面具有端子的衬底可以邻近所述第二层的底部放置，所述后端子被施加到用于n沟道格式的晶体管结构的负电压源。 芯片的半导体材料是从元素周期表第III族和第Ⅴ族元素的化合物得到的。

    Thermally stable low resistance contact
    7.
    发明授权
    Thermally stable low resistance contact 失效
    耐热稳定的低电阻接触

    公开(公告)号：US4849802A

    公开(公告)日：1989-07-18

    申请号：US233851

    申请日：1988-08-16

    申请人： Thomas N. Jackson ,  Masanori Murakami ,  William H. Price ,  Sandip Tiwari ,  Jerry M. Woodall ,  Steven L. Wright

    发明人： Thomas N. Jackson ,  Masanori Murakami ,  William H. Price ,  Sandip Tiwari ,  Jerry M. Woodall ,  Steven L. Wright

    IPC分类号： H01L29/45

    CPC分类号： H01L29/452

    摘要： In a semiconductor device, a contact with low resistance to a III-V compound semiconductor substrate was fabricated using refractory materials and small amounts of indium as the contact material. The contact material was formed by depositing Mo, Ge and W with small amounts of In onto doped GaAs wafers. The contact resistance less than 1.0 ohm millimeter was obtained after annealing at 800.degree. C. and the resistance did not increase after subsequent prolonged annealing at 400.degree. C.

    摘要翻译： 在半导体器件中，使用耐火材料和少量的铟作为接触材料制造具有低耐III-V化合物半导体衬底的接触。 通过将Mo，Ge和W与少量的In沉积到掺杂的GaAs晶片上形成接触材料。 800℃退火后获得小于1.0欧姆毫米的接触电阻，在400℃下经过长时间的退火后，电阻不增加。

    Compound semiconductor interface control
    8.
    发明授权
    Compound semiconductor interface control 失效
    复合半导体接口控制

    公开(公告)号：US4843450A

    公开(公告)日：1989-06-27

    申请号：US874738

    申请日：1986-06-16

    申请人： Peter D. Kirchner ,  Alan C. Warren ,  Jerry M. Woodall ,  Steven L. Wright

    发明人： Peter D. Kirchner ,  Alan C. Warren ,  Jerry M. Woodall ,  Steven L. Wright

    IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L29/45 ,  H01L29/47 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L29/513 ,  H01L21/28264 ,  H01L21/31654 ,  H01L29/456 ,  H01L29/475 ,  H01L29/51

    摘要： Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.

    摘要翻译： 通过在半导体的表面上提供不含阴离子物质的阳离子氧化物以实现平带性能并且将一些阴离子物质局部包含在屏障中来实现费米能级钉扎问题的控制和化合物半导体中的平带表面性能的产生 性能，使得氧化物和金属功能响应性在MOSFET，MESFET和不同功能金属FET结构中的结构和性能方面是可用的。 阳离子氧化镓通过照射期间的氧化物生长和用氧化水冲洗而在GaAs上产生。 氧化用于产生阴离子和阳离子物质，而漂洗过程选择性地除去所有阴离子物质。