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    ATOMIC LAYER DEPOSITION IN THE FORMATION OF GATE STRUCTURES FOR III-V SEMICONDUCTOR
    2.
    发明申请
    ATOMIC LAYER DEPOSITION IN THE FORMATION OF GATE STRUCTURES FOR III-V SEMICONDUCTOR 有权
    形成III-V半导体门结构的原子层沉积

    公开(公告)号：US20080105901A1

    公开(公告)日：2008-05-08

    申请号：US11557354

    申请日：2006-11-07

    申请人： Kamal Tabatabaie ,  Robert B. Hallock

    发明人： Kamal Tabatabaie ,  Robert B. Hallock

    IPC分类号： H01L29/778 ,  H01L21/28

    CPC分类号： H01L21/28587 ,  H01L29/66462

    摘要： A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.

    摘要翻译： 一种半导体结构和方法，其中凹部设置在半导体结构的表面部分中，并且电介质膜设置在半导体上并与其接合。 电介质膜具有孔。 电介质膜的一部分设置成与凹部的孔和悬垂下部相邻。 电触头的第一部分设置在电介质膜的相邻部分上，第二部分设置在凹槽的下面部分上，电介质膜的部分设置在电触点的第一部分和第二部分之间 电接触，并且电接触件的第三部分设置在半导体结构中的凹部的底部上并与其接触。 电接触通过在电介质膜上并通过这种电介质膜中的孔的原子层沉积导电材料形成。

    Atomic layer deposition in the formation of gate structures for III-V semiconductor
    5.
    发明授权
    Atomic layer deposition in the formation of gate structures for III-V semiconductor 有权
    原子层沉积形成III-V半导体栅极结构

    公开(公告)号：US07692222B2

    公开(公告)日：2010-04-06

    申请号：US11557354

    申请日：2006-11-07

    申请人： Kamal Tabatabaie ,  Robert B. Hallock

    发明人： Kamal Tabatabaie ,  Robert B. Hallock

    IPC分类号： H01L29/47

    CPC分类号： H01L21/28587 ,  H01L29/66462

    摘要： A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.

    摘要翻译： 一种半导体结构和方法，其中凹部设置在半导体结构的表面部分中，并且电介质膜设置在半导体上并与其接合。 电介质膜具有孔。 电介质膜的一部分设置成与凹部的孔和悬垂下部相邻。 电触头的第一部分设置在电介质膜的相邻部分上，第二部分设置在凹槽的下面部分上，电介质膜的部分设置在电触点的第一部分和第二部分之间 电接触，并且电接触件的第三部分设置在半导体结构中的凹部的底部上并与其接触。 电接触通过在电介质膜上并通过这种电介质膜中的孔的原子层沉积导电材料形成。

    DIE ALIGNMENT WITH CRYSTALLOGRAPHIC AXES IN GaN-ON-SiC AND OTHER NON-CUBIC MATERIAL SUBSTRATES
    6.
    发明申请
    DIE ALIGNMENT WITH CRYSTALLOGRAPHIC AXES IN GaN-ON-SiC AND OTHER NON-CUBIC MATERIAL SUBSTRATES 审中-公开
    在GaN-SiC中的晶体轴对准其他非基材材料

    公开(公告)号：US20120313111A1

    公开(公告)日：2012-12-13

    申请号：US13154968

    申请日：2011-06-07

    申请人： Robert B. Hallock ,  Paul M. Head

    发明人： Robert B. Hallock ,  Paul M. Head

    IPC分类号： H01L29/12 ,  H01L21/78

    CPC分类号： H01L27/0203 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4238 ,  H01L29/778

    摘要： A semiconductor chip comprises: a semiconductor structure having a single crystal substrate having a non-cubic crystallographic structure and epitaxial layers disposed on the substrate wherein adjacent sides of the semiconductor structure are at oblique angles. A method for separating a plurality of integrated circuit chips. The method includes: providing a semiconductor wafer having single crystal substrate, such substrate having a non-cubic crystallographic structure with an epitaxial layer disposed on the substrate; forming scribe lines at oblique angles to one another in the epitaxial layer; and cutting or cleaving through the substrate along the scribe lines to separate the chips.

    摘要翻译： 半导体芯片包括：半导体结构，具有具有非立方晶体结构的单晶衬底和设置在衬底上的外延层，其中半导体结构的相邻侧是倾斜角。 一种用于分离多个集成电路芯片的方法。 该方法包括：提供具有单晶衬底的半导体晶片，该衬底具有非立方晶系结构，其外延层设置在衬底上; 在外延层中以相互倾斜的角度形成划线; 并沿切割线切割或切割基板以分离芯片。