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1.发明授权公开(公告)号：US07358444B2
公开(公告)日：2008-04-15
申请号：US10964790
申请日：2004-10-13
IPC分类号： H05K1/00
CPC分类号： H01L23/5387 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06579 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/141 , H05K1/147 , H05K1/189 , H05K7/1061 , H05K2201/056 , H05K2201/10378 , H05K2201/10734 , Y10T29/49128 , Y10T29/4913 , Y10T29/49135 , Y10T29/49144 , Y10T29/49146 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer and a substrate folded around the interposer. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，组装包装堆叠包括第一集成电路封装和第二集成电路封装，所述第一集成电路封装使用中介层和围绕插入件折叠的衬底机械地和电连接。 描述和要求保护其他实施例。
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2.发明授权公开(公告)号：US07818878B2
公开(公告)日：2010-10-26
申请号：US12042222
申请日：2008-03-04
IPC分类号： H05K3/30
CPC分类号： H01L23/5387 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06579 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/141 , H05K1/147 , H05K1/189 , H05K7/1061 , H05K2201/056 , H05K2201/10378 , H05K2201/10734 , Y10T29/49128 , Y10T29/4913 , Y10T29/49135 , Y10T29/49144 , Y10T29/49146 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer and a substrate folded around the interposer. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，组装包装堆叠包括第一集成电路封装和第二集成电路封装，所述第一集成电路封装使用中介层和围绕插入件折叠的衬底机械地和电连接。 描述和要求保护其他实施例。
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公开(公告)号：US07304373B2
公开(公告)日：2007-12-04
申请号：US10977908
申请日：2004-10-28
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/5387 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06579 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01077 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A device includes a folded flex substrate. A memory die is connected to a first side of the folded flex substrate. A logic die is connected to a second side of the folded flex substrate. A trace routing pattern of source voltage signals is identical to a trace routing pattern of collector voltage signals.
摘要翻译： 一种装置包括折叠的柔性基底。 存储芯片连接到折叠的柔性基板的第一侧。 逻辑裸片连接到折叠的柔性基板的第二侧。 源电压信号的跟踪路由模式与集电极电压信号的跟踪路由模式相同。
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公开(公告)号：US10446530B2
公开(公告)日：2019-10-15
申请号：US13977101
申请日：2011-08-16
IPC分类号： H05K1/11 , H05K3/40 , H01L25/18 , H01L23/498 , H01L23/00 , H01L25/10 , H01L21/48 , H01L25/00 , H01L25/065
摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
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5.发明申请Use of die backside films to modulate EOL coplanarity of thin packages while providing thermal capability and laser markability of packages 审中-公开使用模具背面薄膜来调节薄封装的EOL共面性，同时提供封装的热性能和激光标记能力公开(公告)号：US20110156283A1
公开(公告)日：2011-06-30
申请号：US12655283
申请日：2009-12-28
申请人： Shankar Ganapathysubramanian , Leonel R. Arana , Robert L. Sankman , Wen Janet Feng , Robert M. Nickerson
发明人： Shankar Ganapathysubramanian , Leonel R. Arana , Robert L. Sankman , Wen Janet Feng , Robert M. Nickerson
CPC分类号： H01L24/81 , H01L21/56 , H01L21/561 , H01L21/6836 , H01L23/295 , H01L23/3121 , H01L23/3157 , H01L23/562 , H01L2221/68327 , H01L2221/68377 , H01L2224/81002 , H01L2224/81193 , H01L2224/814 , H01L2224/81815 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/3511 , H01L2924/00
摘要： A microelectronic package comprises a die (110) having a front side (111) containing active circuitry (115) and a back side (112) opposite the front side and a film (120) on the back side of the die. The film has a thickness (121) of at least 20 micrometers, a Young's modulus of at least 10 GPa, and a post-cure glass transition temperature of at least 100° Celsius.
摘要翻译： 微电子封装包括具有包含有源电路（115）的前侧（111）和与前侧相对的后侧（112）的模具（110）和在模具背面的膜（120）。 膜具有至少20微米的厚度（121），至少10GPa的杨氏模量和至少100℃的后固化玻璃化转变温度。
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公开(公告)号：US08674519B2
公开(公告)日：2014-03-18
申请号：US12971765
申请日：2010-12-17
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/13 , H01L23/3121 , H01L23/49833 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4911 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06568 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/1517 , H01L2924/181 , H01L2924/19107 , H01L2924/15153 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A microelectronic package includes a substrate (110, 210), an interposer (120, 220) having a first surface (121) and an opposing second surface (122), a microelectronic die (130, 230) attached to the substrate, and a mold compound (140) over the substrate. The interposer is electrically connected to the substrate using a wirebond (150). The first surface of the interposer is physically connected to the substrate with an adhesive (160), and the second surface has an electrically conductive contact (126) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.
摘要翻译： 微电子封装包括衬底（110,210），具有第一表面（121）和相对的第二表面（122）的中介层（120,220），附接到衬底的微电子管芯（130,230），以及 模制化合物（140）。 插入器使用引线键（150）与衬底电连接。 插入器的第一表面用粘合剂（160）物理连接到基板，并且第二表面具有形成在其中的导电触点（126）。 模具化合物完全包封引线键并部分地封装插入件，使得插入件的第二表面中的导电接触件保持未被模具化合物覆盖。
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7.发明申请OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES 审中-公开用于大型包装和大型包装包装结构的偏移插件公开(公告)号：US20130271907A1
公开(公告)日：2013-10-17
申请号：US13977101
申请日：2011-08-16
CPC分类号： H01L25/18 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/43 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/89 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/08238 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48245 , H01L2224/48472 , H01L2224/73204 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/143 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1511 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/381 , H05K1/113 , H05K3/4038 , Y10T29/49124 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.
摘要翻译： 偏移插入件包括包括陆侧侧球栅阵列（BGA）和包装袋（POP）侧的陆侧，该侧包括POP侧BGA。 接地侧BGA包括两个相邻的间隔开的陆侧焊盘，并且POP侧BGA包括两个相邻的间隔开的POP侧焊盘，其通过偏移插入件耦合到相应的两个焊盘侧BGA焊盘 。 地面BGA配置为与第一级互连进行接口POP侧BGA配置为与POP基板进行接口。 两个陆侧垫中的每一个具有与相应的两个POP侧垫不同的占地面积。
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公开(公告)号：US20120153504A1
公开(公告)日：2012-06-21
申请号：US12971765
申请日：2010-12-17
CPC分类号： H01L24/49 , H01L23/13 , H01L23/3121 , H01L23/49833 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4911 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06568 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/1517 , H01L2924/181 , H01L2924/19107 , H01L2924/15153 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A microelectronic package includes a substrate (110, 210), an interposer (120, 220) having a first surface (121) and an opposing second surface (122), a microelectronic die (130, 230) attached to the substrate, and a mold compound (140) over the substrate. The interposer is electrically connected to the substrate using a wirebond (150). The first surface of the interposer is physically connected to the substrate with an adhesive (160), and the second surface has an electrically conductive contact (126) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.
摘要翻译： 微电子封装包括衬底（110,210），具有第一表面（121）和相对的第二表面（122）的中介层（120,220），附接到衬底的微电子管芯（130,230），以及 模制化合物（140）。 插入器使用引线键（150）与衬底电连接。 插入器的第一表面用粘合剂（160）物理连接到基板，并且第二表面具有形成在其中的导电触点（126）。 模具化合物完全包封引线键并部分地封装插入件，使得插入件的第二表面中的导电接触件保持未被模具化合物覆盖。
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公开(公告)号：US20090004317A1
公开(公告)日：2009-01-01
申请号：US11772200
申请日：2007-06-30
CPC分类号： C09K5/14
摘要： A molding compound for use in an integrated circuit package comprises an epoxy and a thermally conductive filler material. The thermally conductive filler material comprises between 70% and 95% of the molding compound and has a thermal conductivity between 10 W/m-K and 3000 W/m-K.
摘要翻译： 用于集成电路封装的模塑料包括环氧树脂和导热填料。 该导热填料包含70％至95％的模塑料，其导热率在10W / m-K至3000W / m-K之间。
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公开(公告)号：US20140264910A1
公开(公告)日：2014-09-18
申请号：US13829483
申请日：2013-03-14
申请人： Sandeep Razdan , Edward R. Prack , Sairam Agraharam , Robert L. Sankman , Shan Zhong , Robert M. Nickerson
发明人： Sandeep Razdan , Edward R. Prack , Sairam Agraharam , Robert L. Sankman , Shan Zhong , Robert M. Nickerson
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L25/0657 , C09J9/02 , H01L21/565 , H01L23/3128 , H01L23/49811 , H01L23/49866 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53242 , H01L23/5329 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/95 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/12105 , H01L2224/13005 , H01L2224/13025 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/29078 , H01L2224/2929 , H01L2224/293 , H01L2224/2939 , H01L2224/29411 , H01L2224/29439 , H01L2224/29444 , H01L2224/29447 , H01L2224/29455 , H01L2224/29499 , H01L2224/73104 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2224/83191 , H01L2224/83851 , H01L2224/83856 , H01L2224/83862 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/12042 , H01L2924/15331 , H01L2924/181 , H01L2924/00014 , H01L2224/13611 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13613 , H01L2924/014 , H01L2924/207 , H01L2924/0665 , H01L2924/00
摘要： Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例涉及在集成电路（IC）封装组件中具有聚合物芯的互连结构的技术和配置。 在一个实施例中，一种装置包括具有设置在第一管芯的有源侧上的多个晶体管器件的第一管芯和与第一管芯电耦合的多个互连结构，其中多个互连结构中的各个互连结构具有 聚合物芯和设置在聚合物芯上的导电材料，所述导电材料被配置为在第一管芯的晶体管器件和第二管芯之间布置电信号。 可以描述和/或要求保护其他实施例。
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