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    IMAGER DIE PACKAGE AND METHODS OF PACKAGING AN IMAGER DIE ON A TEMPORARY CARRIER
    2.
    发明申请
    IMAGER DIE PACKAGE AND METHODS OF PACKAGING AN IMAGER DIE ON A TEMPORARY CARRIER 有权
    成像装置的包装和方法在暂时载体上包装成像器

    公开(公告)号：US20090068798A1

    公开(公告)日：2009-03-12

    申请号：US11851787

    申请日：2007-09-07

    申请人： Steven Oliver ,  Warren M. Farnworth

    发明人： Steven Oliver ,  Warren M. Farnworth

    IPC分类号： H01L21/00

    CPC分类号： H01L21/56 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/13

    摘要： Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication substrate comprising a plurality of imager die. Thereafter, known good die (KGD) qualified from the imager die are repopulated, face down on a high temperature-compatible temporary carrier, the KGD on the temporary carrier are encapsulated and thereafter removed as a reconstructed wafer from the temporary carrier. Furthermore, a first plurality of discrete conductive elements on a back side of the reconstructed wafer may be partially exposed and, optionally, a second plurality of discrete conductive elements may be applied to the first plurality of discrete conductive elements. The encapsulated KGD are then singulated.

    摘要翻译： 公开了用于制造成像模具封装件和所得模具封装件的方法。 成像模具封装工艺可以包括通过包括多个成像模具的制造衬底的切割。 此后，从成像模具鉴定出的已知的良好模具（KGD）被重新填充，面向下在高温兼容的临时载体上，临时载体上的KGD被封装，然后从临时载体上移除作为重构的晶片。 此外，在重建的晶片的背侧上的第一多个离散的导电元件可以被部分地暴露，并且可选地，第二多个分立的导电元件可被施加到第一多个分立的导电元件。 然后将封装的KGD分开。

    Imager die package and methods of packaging an imager die on a temporary carrier
    4.
    发明授权
    Imager die package and methods of packaging an imager die on a temporary carrier 有权
    成像仪芯片封装以及在临时载体上封装成像仪的方法

    公开(公告)号：US07923298B2

    公开(公告)日：2011-04-12

    申请号：US11851787

    申请日：2007-09-07

    申请人： Steven Oliver ,  Warren M. Farnworth

    发明人： Steven Oliver ,  Warren M. Farnworth

    IPC分类号： H01L21/56 ,  H01L31/048

    CPC分类号： H01L21/56 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/13

    摘要： Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication substrate comprising a plurality of imager die. Thereafter, known good die (KGD) qualified from the imager die are repopulated, face down on a high temperature-compatible temporary carrier, the KGD on the temporary carrier are encapsulated and thereafter removed as a reconstructed wafer from the temporary carrier. Furthermore, a first plurality of discrete conductive elements on a back side of the reconstructed wafer may be partially exposed and, optionally, a second plurality of discrete conductive elements may be applied to the first plurality of discrete conductive elements. The encapsulated KGD are then singulated.

    摘要翻译： 公开了用于制造成像模具封装件和所得模具封装件的方法。 成像模具封装工艺可以包括通过包括多个成像模具的制造衬底的切割。 此后，从成像模具鉴定出的已知的良好模具（KGD）被重新填充，面向下在高温兼容的临时载体上，临时载体上的KGD被封装，然后从临时载体上移除作为重构的晶片。 此外，在重建的晶片的背侧上的第一多个离散的导电元件可以被部分地暴露，并且可选地，第二多个分立的导电元件可被施加到第一多个分立的导电元件。 然后将封装的KGD分开。

    MICROELECTRONIC DEVICES WITH IMPROVED HEAT DISSIPATION AND METHODS FOR COOLING MICROELECTRONIC DEVICES
    5.
    发明申请
    MICROELECTRONIC DEVICES WITH IMPROVED HEAT DISSIPATION AND METHODS FOR COOLING MICROELECTRONIC DEVICES 有权
    具有改进的散热装置的微电子装置和用于冷却微电子装置的方法

    公开(公告)号：US20130003303A1

    公开(公告)日：2013-01-03

    申请号：US13612337

    申请日：2012-09-12

    申请人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

    发明人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

    IPC分类号： H05K7/20

    CPC分类号： H01L23/367 ,  H01L23/427 ,  H01L24/31 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2224/0401

    摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

    摘要翻译： 本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。 在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。 第二表面具有增加第二表面的表面积的多个传热表面特征。 在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

    WAFER-LEVEL PACKAGED MICROELECTRONIC IMAGERS AND PROCESSES FOR WAFER-LEVEL PACKAGING
    6.
    发明申请
    WAFER-LEVEL PACKAGED MICROELECTRONIC IMAGERS AND PROCESSES FOR WAFER-LEVEL PACKAGING 有权
    水平包装微电子成像器和水平包装的工艺

    公开(公告)号：US20120104528A1

    公开(公告)日：2012-05-03

    申请号：US13349143

    申请日：2012-01-12

    申请人： Salman Akram ,  Peter A. Benson ,  Warren M. Farnworth ,  William M. Hiatt

    发明人： Salman Akram ,  Peter A. Benson ,  Warren M. Farnworth ,  William M. Hiatt

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H04N5/2253 ,  H01L27/14609 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/02325 ,  H01L2224/48091 ,  H04N5/2254 ,  H01L2924/00014

    摘要： The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision.

    摘要翻译： 以下公开内容描述了（1）用于微电子成像器的晶片级封装的方法的几个实施例，（2）在微电子成像器中形成导电互连的方法，（3）用于形成微电子成像器的光学器件的方法，以及（4）微电子 使用晶圆级封装工艺封装的成像仪。 预期微电子成像器的晶片级封装将显着提高制造微电子成像器的效率，因为可以使用开发用于封装半导体器件的高精度和有效的工艺同时封装多个成像器。 此外，微电子成像器的晶片级封装有望提高这种成像器的质量和性能，因为半导体制造工艺可以可靠地将光学器件与图像传感器对准，并将光学器件与图像传感器分开，并将其与图像传感器隔开期望的距离， 更高的精度。

    VERTICAL SURFACE MOUNT ASSEMBLY AND METHODS
    8.
    发明申请
    VERTICAL SURFACE MOUNT ASSEMBLY AND METHODS 审中-公开
    垂直表面安装组件和方法

    公开(公告)号：US20110101514A1

    公开(公告)日：2011-05-05

    申请号：US13005218

    申请日：2011-01-12

    申请人： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

    发明人： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

    IPC分类号： H01L23/34

    CPC分类号： H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

    摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.

    摘要翻译： 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 优选地，半导体器件的至少一部分被暴露。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。