中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.016 seconds)

    Light projection coupling of semiconductor type devices through the use of thermally grown or deposited SiO{HD 2 {B films
    4.
    发明授权
    Light projection coupling of semiconductor type devices through the use of thermally grown or deposited SiO{HD 2 {B films 失效
    通过使用热生长或沉积的SiO {HD 2 {B膜

    公开(公告)号：US3879606A

    公开(公告)日：1975-04-22

    申请号：US40007373

    申请日：1973-09-24

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： BEAN KENNETH E

    IPC: G02B6/42 ,  G02B6/43 ,  H01L27/00 ,  H01L27/144 ,  H01L31/00 ,  G02B5/14 ,  H01L15/00

    CPC classification number: H01L27/00 ,  G02B6/42 ,  G02B6/43 ,  H01L27/1443 ,  H01L31/00

    Abstract: The disclosure relates to a method and system for coupling semiconductor components on a single semiconductor chip or wafer without providing the possibility for short circuits and/or capacitances between metallization layers where connections between one set of components via metallization must pass across the path of connections via metallization to other sets of components. This is accomplished by providing a light conducting path in the semiconductor chip or wafer, such as in the form of a silicon dioxide layer path between the elements to be coupled. A device is provided in the coupling path which is capable of passing a light beam to the elements themselves for activating them, the elements being activated by light impinging on them. The elements are light responsive for actuation, or actuated electrically by another adjacently located light responsive element. The device for providing the light can be a light emitting diode which is externally controlled, a set of mirrors which reflect light from an external laser beam or any other system capable of providing light. The light travels through the silicon dioxide layer which has the properties of a light pipe and will actuate all light responsive semiconductor devices in the crystal to which the path of silicon dioxide is connected. There is no short circuit or stray capacitance problem due to elimination of at least part of the metallization.

    Abstract translation: 本公开涉及用于在单个半导体芯片或晶片上耦合半导体部件的方法和系统，而不提供在金属化层之间的短路和/或电容的可能性，其中，通过金属化之间的一组部件之间的连接必须经过连接路径经过 金属化到其他组件。 这通过在半导体芯片或晶片中提供光传导路径来实现，例如在要耦合的元件之间的二氧化硅层路径的形式。 在耦合路径中设置有能够将光束传递到元件本身以激活它们的装置，该元件被光照射在它们上而被激活。 这些元件对于致动是轻的响应的，或由另一个相邻的光响应元件电驱动。 用于提供光的装置可以是外部控制的发光二极管，一组反射镜，其反射来自外部激光束或能够提供光的任何其他系统的光。 光穿过具有光管性质的二氧化硅层，并且将致动二氧化硅连接路径的晶体中的所有光响应半导体器件。 由于消除至少部分金属化而没有短路或杂散电容问题。

    Deposition reactor
    5.
    发明授权
    Deposition reactor 失效
    沉积反应器

    公开(公告)号：US3608519A

    公开(公告)日：1971-09-28

    申请号：US3608519D

    申请日：1968-12-31

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： BEAN KENNETH E ,  CAMPION JOHN R

    IPC: C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  H01L21/00 ,  B05C11/14

    CPC classification number: C23C16/45563 ,  C23C16/455 ,  H01L21/00

    Abstract: A reactor for depositing a thin layer of material on a semiconductor slice by thermal decomposition of reactant gases is disclosed which has a circular rail, a number of disk-shaped graphite susceptors or supports each having a flat face from which projects a circular retaining rim, a member rotating on an axis extending through the circular rail for rolling the susceptors along the rail while supporting the susceptors at an inclined angle, and an RF coil for heating the susceptors as they are rolled along the rail. The edge of a semiconductor slice placed on the face of the susceptor rolls around the rim of the susceptor as the susceptor rolls. This mechanism is enclosed in a chamber and the reactant gases passed through the chamber. Thus, anomalies in the RF field are compensated as the susceptor rolls around the rail to evenly heat the susceptor, thermal anomalies in the susceptors are compensated as the slice continually moves over the susceptor, and anomalies in the composition of the reactant stream are compensated as each semiconductor slice rotates about its own axis while being translated in a circular path through the vapor stream. Layers uniform in thickness within + OR - 0.5 percent have been achieved, representing an order of magnitude improvement over prior art devices, with corresponding improvements in the uniformity of doping levels and resistivities.

    Method of dielectric isolation to provide backside collector contact and scribing yield
    7.
    发明授权
    Method of dielectric isolation to provide backside collector contact and scribing yield 失效
    电介质隔离方法提供背面集电极接触和划线产量

    公开(公告)号：US3911559A

    公开(公告)日：1975-10-14

    申请号：US42363173

    申请日：1973-12-10

    Applicant: TEXAS INSTRUMENTS INC

    Inventor： BEAN KENNETH E ,  AKRIDGE ALBERT NEAL

    IPC: H01L21/00 ,  H01L21/74 ,  H01L21/762 ,  H01L21/764 ,  H01L29/00 ,  H01L29/04 ,  H01L21/304 ,  H01L21/306 ,  H01L21/36

    CPC classification number: H01L29/045 ,  H01L21/00 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/00 ,  Y10S148/028 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S148/122 ,  Y10S438/928 ,  Y10S438/977

    Abstract: The disclosure relates to a method in bipolar technology of providing a back contact to the collector of a semiconductor device through a dielectrically isolated circuit to reduce saturation resistance and to provide a continuous region of single crystal semiconductor material extending through the entire slice to provide scribe lines extending entirely through the single crystal material to provide much higher scribing yields. The above is provided by depositing an oxide layer over a single crystal substrate and selectively removing portions of the oxide which will later be either scribe points or be positioned beneath the collector of the transistor to be formed. Semiconductor material is then deposited over the oxide layer, this material depositing on the oxide layer and also on the silicon substrate in the region where the oxide has been removed. A buildup will be provided which is polycrystalline over the oxide layer and single crystal over the region wherein the deposited silicon is directly in contact with the silicon substrate. The silicon substrate is then ground and polished back and an epitaxial layer is then deposited thereon. In the case of the scribe lines, an oxide coating is then placed over the topmost semiconductor layer and portions of the oxide are removed over the scribe lines. An orientation dependent etch is then provided through the semiconductor material bound to the scribe lines. Normal scribing techniques could also be used to provide a relatively high yield as compared with the prior art along the scribe lines.

    Abstract translation: 本公开涉及一种双极技术中的方法，其通过介电隔离电路向半导体器件的集电极提供背接触以降低饱和电阻并提供延伸穿过整个切片的单晶半导体材料的连续区域，以提供划线 完全延伸通过单晶材料，以提供更高的划线产量。 通过在单晶衬底上沉积氧化物层并选择性地去除氧化物的部分，这将随后被刻划或者被放置在待形成的晶体管的集电极之下来提供上述。 然后将半导体材料沉积在氧化物层上，该材料沉积在氧化物层上，并且在氧化物被去除的区域中沉积在硅衬底上。 将提供在氧化物层和在其上沉积的硅直接与硅衬底接触的区域上的单晶多晶的堆积。 然后将硅衬底研磨并抛光，然后在其上沉积外延层。 在划线的情况下，然后将氧化物涂层放置在最上面的半导体层上，并且氧化物的部分在划线上被去除。 然后通过结合到划线的半导体材料提供取向相关的蚀刻。 与沿着划线的现有技术相比，正常划线技术也可以用于提供相对高的产量。

Patent Agency Ranking