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39 条记录 (耗时 0.193 秒)

    Manufacture of devices including solder bumps
    6.
    发明授权
    Manufacture of devices including solder bumps 有权
    制造包括焊料凸点的器件

    公开(公告)号：US07727781B2

    公开(公告)日：2010-06-01

    申请号：US12220182

    申请日：2008-07-22

    申请人： Joze Eura Antol ,  Kishor V. Desai ,  John William Osenbach ,  Brian Thomas Vaccaro

    发明人： Joze Eura Antol ,  Kishor V. Desai ,  John William Osenbach ,  Brian Thomas Vaccaro

    IPC分类号： G01L31/26 ,  H01L21/66

    CPC分类号： H05K3/3452 ,  H05K3/3457 ,  H05K2201/099 ,  H05K2203/0271 ,  H05K2203/162

    摘要： Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

    摘要翻译： 焊接接头（例如印刷电路板焊盘处的接头）的典型测试尚未被证明完全可以预测这种接头的最终性能。 已经发现，这种缺乏可靠性至少部分地是由于这些焊盘在测试期间失去与下面的衬底的粘附或分层的倾向。 相比之下，这种情况并不是典型的设备使用期间引起的现象。 为了消除这种不可靠性的原因，测试结构与制造设备批次一起进行。 使用相同的焊盘处理，并且焊盘尺寸在测试结构中大大扩大。 测试结构用于预测批次中的设备的性能，然后相应地处理批次。

    Semiconductor flip chip ball grid array package
    7.
    发明授权
    Semiconductor flip chip ball grid array package 有权
    半导体倒装芯片球栅阵列封装

    公开(公告)号：US06266249B1

    公开(公告)日：2001-07-24

    申请号：US09375835

    申请日：1999-08-16

    申请人： Kishor V. Desai ,  Sunil Patel ,  Ramaswamy Ranganathan

    发明人： Kishor V. Desai ,  Sunil Patel ,  Ramaswamy Ranganathan

    IPC分类号： H05K118

    CPC分类号： H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.

    摘要翻译： 存在半导体封装以及相关方法。 该封装包括具有顶表面和底表面的衬底，该衬底具有从衬底的顶表面延伸到衬底的底表面的多个导电通孔。 具有活性表面的半导体器件，具有多个接合焊盘的活性表面通过与通孔对准的基底孔的粘合剂附着到基底上。 通孔也与焊盘对准。 焊料用于将每个焊盘与相应的通孔电连接和机械耦合。 每个通孔又连接到形成在基底的底部上的焊球。

    Use of blind vias for soldered interconnections between substrates and printed wiring boards
    8.
    发明授权
    Use of blind vias for soldered interconnections between substrates and printed wiring boards 有权
    对基板和印刷电路板之间的焊接互连使用盲孔

    公开(公告)号：US06452116B2

    公开(公告)日：2002-09-17

    申请号：US09796389

    申请日：2001-02-28

    申请人： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffrey S. Perkins ,  John J. Pessarchick

    发明人： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffrey S. Perkins ,  John J. Pessarchick

    IPC分类号： H01R909

    CPC分类号： H05K1/112 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144

    摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.

    摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：将一个或多个盲孔放置在位于第一导体顶部的第一衬底中; 将一个或多个盲孔放置在位于第二导体下方的第二衬底中; 将一个或多个信号线附接到所述一个或多个盲孔中的一个或多个; 以及组装球栅阵列部件，使得第一导体电连接到第二导体。 还要求保护的是一种电子电路封装，其包括用于根据本发明的层之间的电连接的盲孔。

    Interposer for semiconductor package assembly
    9.
    发明授权
    Interposer for semiconductor package assembly 有权
    用于半导体封装组装的插入器

    公开(公告)号：US06335491B1

    公开(公告)日：2002-01-01

    申请号：US09499801

    申请日：2000-02-08

    申请人： Maniam Alagaratnam ,  Kishor V. Desai ,  Sunil A. Patel

    发明人： Maniam Alagaratnam ,  Kishor V. Desai ,  Sunil A. Patel

    IPC分类号： H05K116

    CPC分类号： H05K3/3436 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/284 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/041 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174 ,  H01L2224/0401

    摘要： The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

    摘要翻译： 本发明描述了一种提高半导体器件的热性能的插入器。 插入器可以位于基板和板之间。 插入件连接到两层焊球。 第一层焊球将电介质和机械连接到衬底。 第二层焊球电连接和机械连接插入器到板。 在一个方面，可以灵活地选择中介层的热膨胀系数（CTE），以减小由于衬底与插入件或插入件之间的热性能差异导致的两个或两个焊球层的热应变诱发应力， 板。 在另一方面，可以减小中介层的CTE以允许衬底的较低CTE，这反过来可以降低衬底和附接到衬底的管芯之间的焊球的热应变诱发应力。 有利地，本发明的改进的热性能可以允许更大的基板，更大的管芯，较大的焊球阵列，减少的焊球间距和引脚数远远高于传统的等级，而不会影响半导体器件的可靠性。

    Apparatus and method for improving ball joints in semiconductor packages
    10.
    发明授权
    Apparatus and method for improving ball joints in semiconductor packages 有权
    用于改善半导体封装中的球接头的装置和方法

    公开(公告)号：US06306751B1

    公开(公告)日：2001-10-23

    申请号：US09406308

    申请日：1999-09-27

    申请人： Sunil A. Patel ,  Chok J. Chia ,  Kishor V. Desai

    发明人： Sunil A. Patel ,  Chok J. Chia ,  Kishor V. Desai

    IPC分类号： H01L2144

    CPC分类号： H01L23/49816 ,  H01L21/288 ,  H01L21/4853 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is an apparatus and method for modifying the manufacture of chip carrier bond pads to increase the quality and reliability of semiconductor packages and ball joints in particular. This is accomplished by minimizing the corrosion of the barrier metal layer on the functional bond pads during gold deposition with the use of sacrificial pads electrically connected with the functional bond pads. According to one embodiment of the invention, a semiconductor package has copper conductive pads on a substrate that are exposed through a dielectric. Both functional and sacrificial (nonfunctional) copper conductive pads are provided. A barrier metal layer composed of nickel is electrolessly plated onto these conductive pads, and a bond metal layer of gold is deposited onto the nickel using electroless, generally immersion, gold plating. The surface area of the nickel on the sacrificial pads is less than that on the functional pads, and the nickel on the sacrificial pads corrodes first during electroless gold deposition. Without nickel corrosion on the functional bond pad, gold can more uniformly be deposited on the surface of the nickel layer. A eutectic solderable material placed on the gold can form a uniform bond with the nickel because the nickel on the functional bond pad is largely corrosion free.

    摘要翻译： 提供了一种用于修改芯片载体接合焊盘的制造以提高半导体封装和球接头的质量和可靠性的装置和方法。 这是通过使用与功能接合焊盘电连接的牺牲垫来最小化金沉积期间功能性接合焊盘上的阻挡金属层的腐蚀。 根据本发明的一个实施例，半导体封装在衬底上具有通过电介质暴露的铜导电焊盘。 提供功能和牺牲（非功能）铜导电焊盘。 由镍构成的阻挡金属层被无电镀在这些导电焊盘上，并且使用化学镀，通常浸入镀金将金的粘结金属层沉积到镍上。 牺牲焊盘上的镍的表面积小于功能焊盘上的镍的表面积，并且在无电镀金沉积期间，牺牲焊盘上的镍首先被腐蚀。 在功能性接合焊盘上没有镍腐蚀，金可以更均匀地沉积在镍层的表面上。 放置在金上的共晶可焊材料可以与镍形成均匀的结合，因为功能性接合焊盘上的镍很大程度上是无腐蚀的。