公开(公告)号：US08811030B1

公开(公告)日：2014-08-19

申请号：US13308068

申请日：2011-11-30

申请人： Timothy Phillips ,  Danny Clavette ,  EungSan Cho ,  Chuan Cheah

发明人： Timothy Phillips ,  Danny Clavette ,  EungSan Cho ,  Chuan Cheah

IPC分类号： H05K7/00

CPC分类号： H01L23/49575 ,  H01L21/4832 ,  H01L23/4951 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

摘要翻译： 电路封装包括：电子电路，形成多个引线的导电材料，以及电子电路和多个引线之间的多个连接。 与多个引线（例如，支持高电流吞吐量的低阻抗引线）相关联的导电材料的一部分被去除以适应电子电路的放置。 多个引线中的每一个可以支持高电流。 多个引线之间的多个连接提供电子电路上的电路节点和设置在电子电路封装的平面表面上的焊盘之间的连接。

公开(公告)号：US08786068B1

公开(公告)日：2014-07-22

申请号：US13308052

申请日：2011-11-30

申请人： Timothy A. Phillips ,  Danny Clavette ,  EungSan Cho ,  Chuan Cheah

发明人： Timothy A. Phillips ,  Danny Clavette ,  EungSan Cho ,  Chuan Cheah

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L21/4832 ,  H01L23/4951 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

摘要翻译： 电路封装包括：电子电路，形成多个引线的导电材料，以及电子电路和多个引线之间的多个连接。 与多个引线（例如，支持高电流吞吐量的低阻抗引线）相关联的导电材料的一部分被去除以适应电子电路的放置。 多个引线中的每一个可以支持高电流。 多个引线之间的多个连接提供电子电路上的电路节点和设置在电子电路封装的平面表面上的焊盘之间的连接。

公开(公告)号：US08253224B2

公开(公告)日：2012-08-28

申请号：US12927341

申请日：2010-11-12

申请人： Kunzhong Hu ,  Chuan Cheah

发明人： Kunzhong Hu ,  Chuan Cheah

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.

摘要翻译： 一种用于半导体器件封装的铜带，其具有电连接到管芯电极的触点，电连接到引线框架的脚部分，位于触点和腿部之间并连接到腿部的腹板部分和连接到连接部分的连接区域 网页部分到联系人。 触点包括具有多个结构的主体，多个结构中的每一个具有凹部和相对的凸起，其大致面对模具电极。

公开(公告)号：US20120168926A1

公开(公告)日：2012-07-05

申请号：US13095725

申请日：2011-04-27

申请人： Eung San Cho ,  Chuan Cheah

发明人： Eung San Cho ,  Chuan Cheah

IPC分类号： H01L23/495

CPC分类号： H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface area for thermal dissipation.

摘要翻译： 一个示例性的公开实施例包括被配置为降压转换器的大功率半导体封装，具有具有漏极的顶表面的同步晶体管，具有集成控制晶体管的倒装芯片驱动器集成电路（IC），所述倒装芯片驱动器IC驱动同步 和控制晶体管，以及将同步晶体管的漏极电耦合到与控制晶体管的控制源共享的引线框架的公共部分的导电夹。 以这种方式，与常规封装相比，引线框架和导电夹具通过直接机械连接和大的表面积传导提供有效的电流传导，显着降低封装电阻，外形尺寸，复杂性和成本。 而且，通过在倒装芯片驱动器IC内只集成控制晶体管而不是控制和同步晶体管两者，同步晶体管可以保持分离，简化制造并提供更大的总体表面积用于散热。

公开(公告)号：US20080237829A1

公开(公告)日：2008-10-02

申请号：US12001016

申请日：2007-12-07

申请人： Chuan Cheah ,  Kunzhong Hu

发明人： Chuan Cheah ,  Kunzhong Hu

IPC分类号： H01L23/52

CPC分类号： H01L23/49562 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/00

摘要： A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

摘要翻译： 一种半导体封装，其包括铆接到支柱的引线框架，电连接到半导体管芯的电极。

公开(公告)号：US07301235B2

公开(公告)日：2007-11-27

申请号：US11144169

申请日：2005-06-03

申请人： Christopher P. Schaffer ,  Chuan Cheah ,  Kevin Hu

发明人： Christopher P. Schaffer ,  Chuan Cheah ,  Kevin Hu

IPC分类号： H01L23/34

CPC分类号： H01L25/162 ,  H01L23/5385 ,  H01L24/01 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

摘要翻译： 电路的半导体部分包括在共同的壳体中以平面方式布置的多个倒装芯片器件。 多个倒装芯片器件彼此连接而不引线接合。 公共壳体包括包装结构，该包装结构包括连接部分和至少一个卷筒纸部分，其有助于热管理由多个倒装芯片装置发出的热量，并将倒装芯片装置彼此​​连接。 电路中的无源器件也可以以平面方式布置在公共壳体中。

公开(公告)号：US06586280B2

公开(公告)日：2003-07-01

申请号：US09929317

申请日：2001-08-14

申请人： Chuan Cheah

发明人： Chuan Cheah

IPC分类号： H01L2160

CPC分类号： H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing a semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件包括衬底和支撑在其上的管芯。 衬底在衬底的表面的第一部分上具有至少一个电连接区域。 模具具有由衬底的表面的第二部分支撑的底表面部分。 模具还包括顶表面部分，其包括金属层和在金属层下面的多个半导体元件。 模具的顶表面部分和底表面部分由位于基材表面上方的模具主体部分分开。 符合标准的金属层从模具的顶表面的金属层的至少一部分延伸，并与衬底表面的第一部分上的至少一个电连接区域电接触。

公开(公告)号：US06448643B2

公开(公告)日：2002-09-10

申请号：US09812464

申请日：2001-03-20

申请人： Chuan Cheah ,  Naresh Thapar ,  Srini Thiruvenkatachari

发明人： Chuan Cheah ,  Naresh Thapar ,  Srini Thiruvenkatachari

IPC分类号： H01L2334

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/85207 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

摘要翻译： SO-8型封装包含安装在一个引线框架部分上的控制MOSFET管芯，并且同步MOSFET和肖特基二极管管芯安装在第二引线框架焊盘部分上。 管芯通过引线框架焊盘和引线接合互连，以定义降压转换器电路，并且模具和引线框架焊盘用共同的绝缘外壳包覆成型。

公开(公告)号：US6133632A

公开(公告)日：2000-10-17

申请号：US161790

申请日：1998-09-28

申请人： Christopher Davis ,  Chuan Cheah ,  Daniel M. Kinzer

发明人： Christopher Davis ,  Chuan Cheah ,  Daniel M. Kinzer

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L23/50 ,  H01L25/04 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L23/49562 ,  H01L23/49575 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/49111 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  Y10S257/901

摘要： A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins on its opposite side which are connected to the FET source, the FET gate and the Schottky diode anode respectively by wire bonds. The lead frame and die are molded in an insulated housing and the lead frame pins are bent downwardly to define a surface-mount package.

摘要翻译： MOSFET管芯和肖特基二极管管芯安装在公共引线框架焊盘上，其漏极和阴极分别在焊盘处连接在一起。 垫具有从其一侧延伸的多个销。 引线框架的相对侧有绝缘引脚，分别通过引线连接到FET源极，FET栅极和肖特基二极管阳极。 引线框架和模具被模制在绝缘壳体中，并且引线框架销向下弯曲以限定表面安装封装。

公开(公告)号：US6040626A

公开(公告)日：2000-03-21

申请号：US225153

申请日：1999-01-04

申请人： Chuan Cheah ,  Jorge Munoz ,  Dan Kinzer

发明人： Chuan Cheah ,  Jorge Munoz ,  Dan Kinzer

IPC分类号： H01L21/60 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/40 ,  H01L23/49562 ,  H01L24/36 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40091 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/8547 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107

摘要： A semiconductor package includes a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.

摘要翻译： 半导体封装包括具有底板部分的底部引线框架和从底板部分延伸的至少一个第一端子; 至少一个第二端子与所述第一端子共面; 具有限定漏极连接的底表面的半导体功率MOSFET管芯和顶表面，其上限定限定源极的第一金属化区域和限定栅极的第二金属化区域，所述底表面联接到引线框架的底板， 第一端子电连接到漏极; 铜板，其耦合并跨越限定所述源连接的所述第一金属化区域的主要部分; 并且至少一个梁部分的尺寸和形状被设计成将铜板部分耦合到至少一个第二端子，使得它被电耦合到源极。