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9 条记录 (耗时 0.038 秒)

    Vibratory in-plane tunneling gyroscope
    8.
    发明授权
    Vibratory in-plane tunneling gyroscope 失效
    振动平面内隧道陀螺仪

    公开(公告)号：US06838806B2

    公开(公告)日：2005-01-04

    申请号：US10038530

    申请日：2002-01-02

    申请人： Bee Lee Chua ,  Holden King Ho Li ,  Yuan Xu ,  Francis Eng Hock Tay ,  William Tze-You Chen

    发明人： Bee Lee Chua ,  Holden King Ho Li ,  Yuan Xu ,  Francis Eng Hock Tay ,  William Tze-You Chen

    IPC分类号： G01C19/5726 ,  G01C19/574 ,  H02N1/00

    CPC分类号： G01C19/574 ,  G01C19/5726

    摘要： A gyroscope comprising: a proof mass; a frame supporting the proof mass; a connection arrangement connecting the proof mass and the frame, the connection arrangement having a first stiffness in a first direction and a second stiffness in a second direction substantially perpendicular to the first direction, one of the stiffness being significantly greater than the other stiffness; and a pair of elements adapted to sense relatively motion therebetween in either the first or the second direction. Also disclosed is a gyroscope comprising: a proof mass; a frame supporting the proof mass and connected to only one edge thereof by a connection arrangement extending between the proof mass and the frame in a first direction, the connection arrangement having a first stiffness in the first direction and a second stiffness in a second direction substantially perpendicular to the first direction, the first stiffness being significantly greater than the second stiffness; and a pair of elements adapted to sense relative motion therebetween in the first direction.

    Miniaturized chip scale ball grid array semiconductor package
    9.
    发明授权
    Miniaturized chip scale ball grid array semiconductor package 有权
    小型化芯片级球栅阵列半导体封装

    公开(公告)号：US06429530B1

    公开(公告)日：2002-08-06

    申请号：US09184839

    申请日：1998-11-02

    申请人： William Tze-You Chen

    发明人： William Tze-You Chen

    IPC分类号： H01L2348

    CPC分类号： H01L24/73 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    摘要： A semiconductor package arrangement and, more particularly, a light weight and miniaturized electronic package or module, wherein the dimensions between an integrated circuit comprising a semiconductor chip and those of a chip carrier have been optimized in order to provide for minimum weight and size relationships. Furthermore, disclosed is a method of forming the semiconductor package arrangement so as to produce a small, lightweight and essentially miniaturized chip-sized chip carrier package module. The chip carrier, which may be an organic laminate, multi-layer ceramic substrate or flexible substrate, as required by specific applications, is basically designed to possess overall smaller peripheral dimensions than those of the integrated circuit or semiconductor chip which is adapted to be mounted thereon. In essence, the chip carrier or substrate is electrically connected to the semiconductor chip through the intermediary of either solder bumps or a conductive adhesive, or other suitable flip chip connection methods. The utilization of an electronic package arrangement which comprises the mounting of a chip on a chip carrier or substrate, wherein the latter is of smaller peripheral dimensions than the semiconductor chip, and thereby eliminates in particular the edge stresses generated by the differentials in thermal expansion between the chip and chip carrier substrate, and in effect, reducing the previously generally encountered high mechanical stresses and extensive heat-induced warpage leading to potential failure of the electrical interconnects or solder joints.

    摘要翻译： 一种半导体封装装置，更具体地说，是一种重量轻且小型化的电子封装或模块，其中包括半导体芯片的集成电路与芯片载体的集成电路之间的尺寸已被优化，以便提供最小的重量和尺寸关系。 此外，公开了一种形成半导体封装布置的方法，以便产生小型，重量轻且基本上小型化的芯片尺寸的芯片载体封装模块。 根据具体应用，可以是有机层压体，多层陶瓷基板或柔性基板的芯片载体基本上被设计为具有比适于安装的集成电路或半导体芯片的整体尺寸更小的外围尺寸 上。 本质上，芯片载体或衬底通过焊料凸块或导电粘合剂或其它合适的倒装芯片连接方法电连接到半导体芯片。 利用包括在芯片载体或衬底上安装芯片的电子封装装置，其中后者的尺寸小于半导体芯片的外围尺寸，从而特别消除了由半导体芯片之间的热膨胀差异产生的边缘应力 芯片和芯片载体衬底，并且实际上减少了先前通常遇到的高机械应力和广泛的热引起的翘曲，导致电互连或焊点的潜在故障。