公开(公告)号：WO2006044219A2

公开(公告)日：2006-04-27

申请号：PCT/US2005035962

申请日：2005-10-06

Applicant: TESSERA INC ,  HUMPSTON GILES ,  MCWILIAMS BRUCE M

Inventor： HUMPSTON GILES ,  MCWILIAMS BRUCE M

IPC: H01L21/50 ,  B81B7/00 ,  G01N21/59

CPC classification number: B81B7/0077 ,  G01N21/3504 ,  H01L21/50 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic package may include front and rear covers (46', 60') overlying the front and rear surfaces of a microelectronic element (22') such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector (76) spaced from the front cover to provide an analyte space, and the microelectronic element may include an emitter (28) and a detector (30) so that radiation directed from the emitter will be reflected by the sensor to the detector, and such radiation will be affected by the properties of the analyte in the analyte space. Such a unit provides a compact, economical chemical sensor. Other packages include elements such as valves (515, 521) for passing fluids into and out of the spaces within the package itself.

Abstract translation: 微电子封装可以包括覆盖诸如红外传感器的微电子元件（22'）的前表面和后表面的前盖和后盖（46'，60'），以及微电子元件和盖之间的空间以提供热隔离。 包括微电子封装的感测单元可以包括与前盖间隔开以提供分析物空间的反射器（76），并且微电子元件可以包括发射器（28）和检测器（30），使得从发射器引导的辐射将 被传感器反射到检测器，并且这种辐射将受分析物空间中分析物的性质的影响。 这种单元提供了紧凑，经济的化学传感器。 其他包装包括诸如用于将流体进入和流出包装内的空间的阀（515,521）的元件。

公开(公告)号：WO2006020488A1

公开(公告)日：2006-02-23

申请号：PCT/US2005/027748

申请日：2005-08-02

Applicant: TESSERA, INC. ,  HABA, Belgacem ,  BEROZ, Masud ,  TUCKERMAN, David B. ,  HUMPSTON, Giles ,  CRISP, Richard D.

Inventor： HABA, Belgacem ,  BEROZ, Masud ,  TUCKERMAN, David B. ,  HUMPSTON, Giles ,  CRISP, Richard D.

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/041 ,  H05K3/06 ,  H05K3/202 ,  H05K3/4038 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09827 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate (10) is included having opposing surfaces and a plurality of holes (12A-D) extending through the surfaces. Also included is a plurality of electrically conductive posts (18A-D). Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate (20) may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts (28A-D) may be provided having tips in corresponding holes (22A-D) of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.

Abstract translation: 提供了用于微电子器件的连接结构和用于形成结构的方法。 包括具有相对表面的基板（10）和延伸穿过表面的多个孔（12A-D）。 还包括多个导电柱（18A-D）。 每个柱从基部延伸到位于基板的相应孔内的尖端。 可以设置另外的基板（20），使得每个柱的基部位于其表面上。 可以在附加基板的相应孔（22A-D）中提供附加的导电柱（28A-D）。 可选地，介电材料可以放置在基板和柱之间。

公开(公告)号：WO2005065207A2

公开(公告)日：2005-07-21

申请号：PCT/US2004/042415

申请日：2004-12-16

Applicant: TESSERA, INC. ,  HABA, Belgacem ,  BEROZ, Masud ,  GREEN, Ronald ,  MOHAMED, Ilyas ,  WILSON, Stuart, E. ,  ZOHNI, Wael ,  KUBOTA, Yoichi ,  THOMPSON, Jesse, Burl

Inventor： HABA, Belgacem ,  BEROZ, Masud ,  GREEN, Ronald ,  MOHAMED, Ilyas ,  WILSON, Stuart, E. ,  ZOHNI, Wael ,  KUBOTA, Yoichi ,  THOMPSON, Jesse, Burl

IPC: H01L21/44

CPC classification number: H01L23/49811 ,  G01R1/06744 ,  G01R1/0735 ,  H01L21/563 ,  H01L23/4985 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13187 ,  H01L2224/13188 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/17 ,  H01L2224/1703 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A microelectronic package includes a microelectronic element (80) having faces and contacts (83) and a flexible substrate (90) spaced from and overlying a first face (84) of the microelectronic element (82). The package (80) also includes a plurality of conductive posts (98) extending from the flexible substrate (90) and projecting away from the first face (84) of the microelectronic element (82), wherein at least some of the conductive posts (98) are electrically interconnected with the microelectronic element (82), and a plurality of support elements (88) supporting the flexible substrate (90) over the microelectronic element (82). The conductive posts (98) are offset from the support elements (82) to facilitate flexure of the substrate (90) and movement of the posts (98) relative to the microelectronic element (82).

Abstract translation: 微电子封装包括具有面和触点（83）的微电子元件（80）和与微电子元件（82）的第一面（84）间隔开并且覆盖其上的柔性基板（90）。 包装（80）还包括从柔性基板（90）延伸并远离微电子元件（82）的第一面（84）突出的多个导电柱（98），其中至少一些导电柱（ 98）与微电子元件（82）电互连，以及支撑微电子元件（82）上的柔性基板（90）的多个支撑元件（88）。 导电柱（98）从支撑元件（82）偏移，以便于衬底（90）的挠曲和柱（98）相对于微电子元件（82）的移动。

公开(公告)号：WO2004034434A3

公开(公告)日：2004-04-22

申请号：PCT/US2003/032078

申请日：2003-10-10

Applicant: TESSERA, INC.

Inventor： KIM, Young-Gon ,  GIBSON, David ,  WARNER, Michael ,  DAMBERG, Philip ,  OSBORN, Philip

IPC: H01L23/34

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer (350) having arranged on a top surface (351) and a bottom surface (352) thereof a number of packaged semiconductor chips (315, 320, 325, 330) mounted via solder bumps (335) in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

公开(公告)号：WO2004034434A2

公开(公告)日：2004-04-22

申请号：PCT/US0332078

申请日：2003-10-10

Applicant: TESSERA INC

Inventor： KIM YOUNG-GON ,  GIBSON DAVID ,  WARNER MICHAEL ,  DAMBERG PHILIP ,  OSBORN PHILIP

IPC: H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H01L

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer (350) having arranged on a top surface (351) and a bottom surface (352) thereof a number of packaged semiconductor chips (315, 320, 325, 330) mounted via solder bumps (335) in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract translation: 具有独立测试和修复功能的超薄系统级封装（SIP）包括布置在多个封装半导体芯片（315）的顶表面（351）和底表面（352）上的插入器（350） ，320,325,330），其经由焊盘（335）安装，所述焊料凸块（335）根据陆地网格阵列（LGA）格式，并且其中在所述SIP上不使用底部填充物。

公开(公告)号：WO2004025699A2

公开(公告)日：2004-03-25

申请号：PCT/US2003/028041

申请日：2003-09-08

Applicant: TESSERA, INC.

Inventor： KANG,teck-Gyu ,  KUBOTA, Yoichi

IPC: H01L

CPC classification number: H01L25/18 ,  H01L25/0657 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A stacked microelectronic assembly comprises a continuous sheet (20) including a core panel (26) and a plurality of side panels (28, 30, 32, 34), each having a folded portion (28a’, 30a’, 32a’, 34a’) that connects the side panel to an edge of the core panel. At least two of the panels are at least partially horizontally aligned with one another in a stack. During manufacture of a stacked microelectronic assembly, failed microelectronic elements are identified and associated side panels thereof are simply cut-off. This results in the production of a usable stacked microelectronic assembly albeit of reduced capacity, or reduced functionality.

Abstract translation: 一种堆叠式微电子组件包括：包括芯板（26）和多个侧板（28,30,32,34）的连续板（20），每个侧板具有折叠部分（28a' ，30a'，32a'，34a'），其将所述侧板连接到所述核心板的边缘。 至少两个面板彼此至少部分地水平对齐成堆叠。 在堆叠式微电子组件的制造过程中，识别失效的微电子元件并且简单地切断其相关联的侧面板。 这导致生产可用的堆叠微电子组件，尽管其容量减少或功能降低。

公开(公告)号：WO2004023546A1

公开(公告)日：2004-03-18

申请号：PCT/US2003/027953

申请日：2003-09-05

Applicant: TESSERA, INC.

Inventor： BANG, Kyong-Mo ,  KANG, Teck-Gyu

IPC: H01L21/48

CPC classification number: H01L24/97 ,  H01L23/3121 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49135 ,  Y10T29/49169 ,  Y10T29/53174 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A microelectronic package 10 is fabricated by a process which included folding a substrate 20. The substrate 20 is folded by engaging a first end 23 of the substrate 20 with a die 60 so that the first end 23 pivots with respect to a central portion 22 of the substrate 20. Next, a second end 24 of the substrate 20 is folded similar to the first end 23.

Abstract translation: 通过包括折叠基板20的工艺制造微电子封装10.通过将基板20的第一端23与模具60接合来折叠基板20，使得第一端部23相对于基板20的中心部分22枢转 接下来，衬底20的第二端24被折叠成类似于第一端23。

公开(公告)号：WO2004017399A1

公开(公告)日：2004-02-26

申请号：PCT/US2003/025256

申请日：2003-08-13

Applicant: TESSERA, INC.

Inventor： BANG, Kyong-Mo ,  KANG, Teck-Gyu ,  PARK, Jae, M.

IPC: H01L21/60

CPC classification number: H01L23/3121 ,  H01L23/4985 ,  H01L23/544 ,  H01L24/48 ,  H01L25/105 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/48472 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package is made by a process which includes folding a substrate (20). Alignment elements (54, 58) on different parts of the substrate (20) engage one another during the folding process to position the parts of the substrate (20) precisely relative to one another. One or more of the alignment elements (54, 58) may be a mass of an overmolding encapsulant covering a chip.

Abstract translation: 微电子封装通过包括折叠衬底（20）的工艺制成。 在折叠过程中，衬底（20）的不同部分上的对准元件（54,58）彼此接合，以便相对于彼此精确地定位衬底（20）的部分。 一个或多个对准元件（54,58）可以是覆盖芯片的包覆成型密封剂的质量。

公开(公告)号：WO2003021673A1

公开(公告)日：2003-03-13

申请号：PCT/US2002/027509

申请日：2002-08-28

Applicant: TESSERA, INC. ,  WARNER, Michael

Inventor： WARNER, Michael

IPC: H01L23/48

CPC classification number: G06F21/10 ,  G06F2221/2129 ,  H01F17/0033 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/5387 ,  H01L23/552 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/6611 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45099 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03H9/0542 ,  H03H9/0547 ,  H03H9/1064 ,  H03H2009/0019 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A packaged semiconductor chip includes features such as a chip carrier (616) having a large thermal conductor (620) which can be solder-bonded to a circuit board so as to provide enhanced thermal conductivity to the circuit board and electromagnetic shielding and a conductive enclosure (671) which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip (614) and a passive element (615), desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier. A module includes two circuits and an enclosure with a medial wall between the circuits to provide electromagnetic shielding between the circuits.

Abstract translation: 封装的半导体芯片包括诸如具有大的热导体（620）的芯片载体（616）的特征，所述大的热导体（620）可以被焊接结合到电路板以便为电路提供增强的导热性 板和电磁屏蔽以及部分或完全围绕封装芯片以提供附加散热和屏蔽的导电外壳（671）。 封装单元可以包括有源半导体芯片（614）和无源元件（615）两者，期望为芯片形式，其包括电阻器和电容器。 电感器可以全部或部分地设置在芯片载体上。 一个模块包括两个电路和一个在电路之间具有内壁的外壳，以在电路之间提供电磁屏蔽。

公开(公告)号：WO1996002068A1

公开(公告)日：1996-01-25

申请号：PCT/US1995008182

申请日：1995-06-29

Applicant: TESSERA, INC.

Inventor： TESSERA, INC. ,  DISTEFANO, Thomas, H. ,  SMITH, John, W.

IPC: H01L21/60

CPC classification number: H01L23/4985 ,  H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49158 ,  H01L2924/00 ,  H01L2224/48

Abstract: A microelectronic connection component includes a dielectric sheet (34) having an area array of elongated, strip-like leads (60). Each lead has a terminal end (66) fastened to the sheet and a tip end (68) detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer (86). The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.

Abstract translation: 微电子连接部件包括具有细长带状引线（60）的区域阵列的电介质片（34）。 每个引线具有紧固到片材的末端（66）和可从片材上拆卸的尖端（68）。 每个引线从其终端到其尖端水平平行地延伸。 尖端附接到第二元件，例如另一个电介质片或半导体晶片（86）。 然后，第一和第二元件相对于彼此移动，以使每个引线的尖端垂直远离电介质片，并将引线变形成弯曲的垂直广泛配置。 优选的结构提供半导体芯片组件，其具有在芯片上的平面区域阵列的触点，片材上的端子阵列被定位成使得每个端子基本上在相应的触点上方，以及连接在端子之间的金属S形带阵列 和联系人。 柔性电介质材料可以设置在片和芯片之间，基本上围绕S形带。