公开(公告)号：WO2006044061A3

公开(公告)日：2009-04-09

申请号：PCT/US2005032386

申请日：2005-09-09

Applicant: ATMEL CORP

Inventor： LAM KEN M

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48669 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48769 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48869 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85469 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/00012

Abstract: An electrical package for an integrated circuit die (101) which comprises a die-attach paddle (201) for mounting the integrated circuit die (101). The die­-attach paddle (201) has at least one down-set area located on a periphery of the die-attach paddle (201). The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire (301). A second end of the first electrically conductive lead wire (301) is bonded to the integrated circuit die (101). The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire (303) and a second end of the second electrically conductive lead wire (303) is bonded to a lead finger (203) of the electrical package.

Abstract translation: 一种用于集成电路管芯（101）的电气封装件，包括用于安装集成电路管芯（101）的管芯附着焊盘（201）。 管芯附着桨（201）具有位于管芯附着桨（201）的周边上的至少一个下降区域。 下降区域具有上表面和下表面，其中上表面被配置为电耦合第一导电引线（301）的第一端。 第一导电引线（301）的第二端接合到集成电路管芯（101）。 上表面还被配置为电耦合第二导电引线（303）的第一端并且第二导电引线（303）的第二端被接合到电气封装的引线指（203）。

公开(公告)号：WO2008008581A2

公开(公告)日：2008-01-17

申请号：PCT/US2007070612

申请日：2007-06-07

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L29/76 ,  H01L23/02

CPC classification number: H01L23/5227 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for producing passive components on an integrated circuit device (100). The integrated circuit device (100) has post wafer fabrication integrated passive components (107) situated on the opposite substrate side (105) of the device's integrated circuitry (103). Electrical contact pads (109) of the passive components (107) are configured to be coupled to the electronics package contact pads to complete the electronic package.

Abstract translation: 一种用于在集成电路器件（100）上产生无源部件的设备和方法。 集成电路器件（100）具有位于器件集成电路（103）的相对衬底侧（105）上的后置晶片制造集成无源部件（107）。 无源部件（107）的电接触垫（109）被配置为耦合到电子封装接触垫以完成电子封装。

公开(公告)号：WO2008008587A2

公开(公告)日：2008-01-17

申请号：PCT/US2007071079

申请日：2007-06-13

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for producing three- dimensional integrated circuit packages. In one embodiment, an electronics package (200) with at least two dice (207, 209) are stacked one atop another is disclosed. A top die (209) is of smaller size compared with a bottom die (207) such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die (207) contains contact pads (211) on the front side that couple with one or more passive components (213) fabricated on the back side of the top die (209) to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract translation: 一种用于生产三维集成电路封装的装置和方法。 在一个实施例中，公开了具有至少两个骰子（207,209）的电子封装（200）。 与底模（207）相比，顶模（209）尺寸较小，使得在芯片附接操作之后，底模的引线接合焊盘将被暴露以用于随后的引线接合操作。 底模（207）包括在前侧上的与在顶模（209）的背面上制造的一个或多个无源元件（213）耦合以便完成电路的接触焊盘（211）。 在另一个示例性实施例中，公开了一种在堆叠管芯封装中形成一个或多个三维无源部件的方法，其中部分电感器元件制造在底模的前侧和顶模的背面。 顶部和底部元件联接在一起，完成无源部件。

公开(公告)号：WO2005034178A2

公开(公告)日：2005-04-14

申请号：PCT/US2004028495

申请日：2004-09-02

Applicant: ATMEL CORP

Inventor： LAM KEN M ,  KOVATS JULIUS A

IPC: H01L21/673 ,  H01L21/687 ,  H01L

CPC classification number: H01L21/68778 ,  G01R1/0483 ,  H01L21/67346 ,  H01L21/68785

Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier (100) for temporarily mounting a non-wafer form device. The low-profile carrier (100) holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses (105, 107) which are machined or otherwise formed in the low-profile carrier (100).

Abstract translation: 本发明允许在标准自动晶片 - 探针测试器或半导体或相关行业（例如，平板显示器，数据存储等）过程中常用的其他自动化测试或测量设备上测试非晶片形式的器件。 本发明通过提供用于临时安装非晶片形式装置的低轮廓载体（100）来实现这一点。 低轮廓载体（100）将非晶片形成装置（例如集成电路芯片，薄膜头结构，一个或多个模制阵列封装等）磁性地保持在机加工的凹部（105,107）中 或以其他方式形成在薄型载体（100）中。

公开(公告)号：WO0182361A3

公开(公告)日：2002-05-16

申请号：PCT/US0111035

申请日：2001-04-04

Applicant: ATMEL CORP

Inventor： LAM KEN M

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/4985 ,  H01L24/02 ,  H01L24/06 ,  H01L24/11 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06102 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01043 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming an integrated circuit package at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. Solder bumps (30), or conductive adhesive, is deposited on the metallized wirebond pads (23) on the top surface of a silicon wafer (21). An underfill-flux material (27) is deposited over the wafer (21) and the solder bumps (30). A pre-fabricated interposer substrate (31), made of a metal circuitry (34) and a dielectric base (32), has a plurality of metallized through-holes (38) which are aligned with the solder bumps (30). The wafer/interposer assembly is reflowed, or cured, to form the electrical connection between the circuitry on the interposer layer (34) and the circuitry on the wafer. Solder balls (50) are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Abstract translation: 一种在晶片级形成集成电路封装的方法。 集成电路封装在最终用途的印刷电路板上占用最小的空间。 焊料凸块（30）或导电粘合剂沉积在硅晶片（21）的顶表面上的金属化引线焊盘（23）上。 在晶片（21）和焊料凸块（30）上沉积底部填充助焊剂材料（27）。 由金属电路（34）和电介质基底（32）制成的预制插入器基板（31）具有与焊料凸块（30）对准的多个金属化通孔（38）。 晶片/插入器组件被回流或固化，以形成插入层（34）上的电路与晶片上的电路之间的电连接。 然后将焊球（50）放置在插入器基板上的金属焊盘开口上并被回流以形成晶片级BGA结构。 然后将晶片级BGA结构切割成单独的BGA芯片封装。

公开(公告)号：WO0167511A3

公开(公告)日：2002-02-07

申请号：PCT/US0100828

申请日：2001-01-10

Applicant: ATMEL CORP

Inventor： LAM KEN M

IPC: H01L25/18 ,  H01L21/301 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012

Abstract: A wafer level packaging method which produces a stacked dual/multiple die integrated circuit package (91). In the method, the wafer with the smaller sized dice (15) of two wafers is processed through a metal redistribution process and then solder balls are attached. The wafer is then sawed into individual die size ball-grid array packages. On the wafer with the larger sized dice (25), a die attached adhesive material (18) is deposited on the front of each die site location that is intended for the attachment of one of the die-sized BGA packages. The back side of the BGA die package is placed onto the adhesive material and is cured. A wirebonding operation connects the signals from the die-size BGA package to the circuits of the bottom die. A coating material (80), such as epoxy, is disposed on the wafer to cover the wirebond leads and the assembly is then cured. Then, the stacked-die wafer is singulated into individual stacked-die IC packages (91).

Abstract translation: 一种晶片级封装方法，其制造堆叠的双/多芯片集成电路封装（91）。 在该方法中，通过金属再分布工艺处理具有两个晶片的较小尺寸的骰子（15）的晶片，然后连接焊球。 然后将晶片锯成单个管芯尺寸的球栅阵列封装。 在具有较大尺寸的骰子（25）的晶片上，将模具附着的粘合剂材料（18）沉积在每个模具位置的前面，用于附接模具尺寸的BGA封装之一。 将BGA封装的背面放置在粘合剂材料上并固化。 引线键合操作将来自模块尺寸BGA封装的信号连接到底模的电路。 将诸如环氧树脂的涂层材料（80）设置在晶片上以覆盖引线引线，然后固化组件。 然后，将堆叠的芯片晶片分割成单独的堆叠管芯IC封装（91）。

公开(公告)号：WO2008008586A3

公开(公告)日：2008-05-02

申请号：PCT/US2007070994

申请日：2007-06-12

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An apparatus and a method for packaging semiconductor devices (205, 207). Disclosed are multi- die packaging apparatuses (200) and techniques, especially useful for integrated circuit dice (207) involving insulative substrates (225), such as silicon- on-insulator (SOI), where grounding of a base layer (225) is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device (205, 207) regardless of whether the device (205, 207) makes direct contact with a die-attach paddle (201).

Abstract translation: 一种封装半导体器件的装置和方法（205,207）。 公开了多芯片封装装置（200）和技术，尤其可用于涉及绝缘衬底（225）的绝缘衬底（225）（例如绝缘体上硅（SOI））的集成电路裸片（207），其中基底层 不合理实际。 公开了一种用于有效地将集成电路器件（205,207）的所有层接地的装置，而不管器件（205,207）是否与管芯附接板（201）直接接触。

公开(公告)号：WO2007127739A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067315

申请日：2007-04-24

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for packaging semi-conductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels (213) formed through an encapsulation area (215) surrounding the device (207) and associated bond wires (211) are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads (205) to an uppermost portion of the encapsulated area (215) . The sacrificial metal base strip (201) serves as a plating bus and is etch-removed after plating. The filled tunnels (213) allow components to be stacked in a three-dimensional configuration.

Abstract translation: 一种用于封装半导体器件的装置和方法。 该设备适用于许多类型的使用牺牲金属基底条的当代包装方案。 通过围绕设备（207）和相关联的接合线（211）的封装区域（215）形成的隧道（213）通过例如电镀被金属导体填充，并将底部接触焊盘（205）延伸到最上部 的封装区域（215）。 牺牲金属基带（201）用作电镀母线，并且在电镀之后被蚀刻去除。 填充的隧道（213）允许组件以三维配置堆叠。

公开(公告)号：WO2005112114A3

公开(公告)日：2006-01-12

申请号：PCT/US2005014139

申请日：2005-04-26

Applicant: ATMEL CORP

Inventor： LAM KEN M ,  KOVATS JULIUS A

IPC: H01L23/14 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/06 ,  H01L23/147 ,  H01L23/49531 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A device (100) for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device (100) has a substrate (111) with a plurality of substantially concentric electrically-conductive paths (101, 103, 105, 107), each of the plurality of electrically-conductive paths (101, 103, 105, 107) being electrically isolated from each other and formed on a first surface of the substrate (111). At least one (107) of the plurality of electrically-conductive paths (101, 103, 105, 107) is arranged concentrically so as to substantially span a width of the first surface of the substrate (111). A plurality of bonding pads (109) is electrically coupled to each of the electrically­conductive paths (101, 103, 105, 107). The plurality of bonding pads is coupled to one of the electrically­ conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path (101, 103, 105, 107). The entire interconnect device (100) may be mounted in a standard leadframe product.

Abstract translation: 一种用于电连接一个或多个半导体器件以提供布线灵活性并防止长引线或短接引线的器件（100）及其制造和使用方法。 所述装置（100）具有多个基本上同心的导电路径（101,103,105,107）的基板（111），所述多个导电路径（101,103,105,107）中的每一个都是 彼此电隔离并形成在基板（111）的第一表面上。 多个导电路径（101,103,105,107）中的至少一个（107）同心地布置，以便基本跨越衬底（111）的第一表面的宽度。 多个接合焊盘（109）电耦合到每个导电路径（101,103,105,107）。 多个接合焊盘耦合到一个导电路径，并且与位于任何其它导电路径（101,103,105,107）上的焊盘电隔离。 整个互连设备（100）可以安装在标准引线框产品中。

公开(公告)号：WO0143193B1

公开(公告)日：2002-05-30

申请号：PCT/US0041466

申请日：2000-10-23

Applicant: ATMEL CORP

Inventor： KOVATS JULIUS A ,  LAM KEN M

IPC: H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L23/49575 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A dual-die integrated circuit package (10) having two integrated circuit chips (14, 16) "flip chip" attached to each other and with one of the chips (14) being aligned at a specified angle in relation to the other chip (16) to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip. Also, being able to use two chips that are identically constructed from a wafer fabrication standpoint provides the advantage of requiring only one IC design process.

Abstract translation: 一种双管芯集成电路封装（10），具有彼此附接的两个集成电路芯片（14,16）“倒装芯片”，并且其中一个芯片（14）相对于另一个芯片以特定角度对准 16）以允许访问每个芯片表面上的键合焊盘，用于引线键合连接到芯片封装中。 在第一实施例中，这两个芯片的形状是矩形的，并且相对于彼此以90度的角度对齐，从而允许底部芯片的端部可接入以连接到芯片封装中。 其他实施例将芯片维持在小于90度的角度，使得每个芯片的角部可被接入以连接到芯片封装中。 本发明允许两个相同构造的芯片用于IC封装的功能或存储器的倍增或甚至更大倍增，同时仍然使用与单个芯片相同的封装占位面积。 而且，能够使用从晶圆制造观点相同构造的两个芯片提供了仅需要一个IC设计过程的优点。