Abstract:
A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.
Abstract:
A method of making a planar, subsurface electronic circuit having at least one electronic circuit component assembled therewith comprises forming three dimensional, essentially square channels (14) interspersed with lands within a dielectric material (12) on a substrate (10). The channels are then filled in one pass with a curable polymeric material (16) containing a conductive metal filler so that the upper surfaces of the circuit trace formed by this conductive material are at essentially the same level as the upper surface of the lands. Circuit components (20) are placed to engage the conductive material. The curable material is then cured after placing the electronic component(s).
Abstract:
An electronic device (10) is made by a method of connecting a circuit member (18) to a substrate (12). The circuit member has a discontinuous passivating layer (20) with recesses therein establishing electrical contacts. The member is connected to a mounting surface (14) of a substrate having conductive paths (16). An adhesive (26) including a resin with spaced conductive metal particles suspended therein is applied over the conductive paths. The distance between electrical contacts (22) and the conductive paths is decreased to provide electrical conduction through the adhesive, while maintaining the adhesive between conductive paths non-conductive. The conductive paths may have established thereon raised or protruding contact surfaces (24) over a portion thereof. The member is mounted on the adhesive while vertically aligning the contacts over preselected protruding contact surfaces. Pressure is applied to concentrate the conductive metal particles between the contacts and conductive paths allowing conduction therethrough.
Abstract:
Improved methods of preparing molded thermoplastic articles are provided. The methods are basically comprised of the steps of admixing a radio frequency energy sensitizing agent comprised of N-ethyl toluenesulfonamide with a thermoplastic polymer, applying radio frequency energy to the mixture formed for a time sufficient to produce a moldable consistency in the mixture, and then compression molding the mixture to produce a molded article therefrom.
Abstract:
Selon un procédé de soudage des connexions de composants (3) pour montage en surface sur une carte de circuits imprimés (1), on forme sur la carte de circuits imprimés (1) une structure en surface telle que des dépressions sont situées aux endroits où les connexions doivent être soudées. Les composants (3) pour montage en surface sont posés avec leurs connexions (31) dans les dépressions remplies de soudure.
Abstract:
Le procédé décrit consiste, dans une première étape, à fabriquer un premier panneau de carte (10) possédant une première configuration de circuit (15) électroconducteur en relief, partant d'une couche de base (14) de matériau conducteur, et une deuxième configuration de circuit (20) électroconducteur en relief, partant de la première configuration de circuit (15). On fabrique ensuite un deuxième panneau de carte (30) présentant une troisième configuration de circuit (35) électroconducteur en relief, qui part d'une autre couche de base (34) de matériau conducteur. Le premier panneau de carte (10) est stratifié sur le deuxième panneau de carte (30), un matériau isolant (40) étant disposé entre les deux pour isoler électriquement la première configuration de circuit (15) de la troisième configuration de circuit (35), la deuxième configuration de circuit (20) étant en contact électrique avec la première configuration de circuit (15) à des emplacements choisis de celui-ci. Pour finir, les couches de base (14, 34) de matériau conducteur sont ôtées du matériau isolant stratifié (40).
Abstract:
Circuit boards that permit wave soldering of both leaded and surface mounted components to a common side. The circuit board carries plated grooves to provide interconnections between the components to be mounted to the board. For leaded components on the circuit board, holes are provided extending completely through the board, and the leaded components are mounted and soldered in a conventional fashion. For surface mounted (or leadless) components, small recesses or grooves are provided to accept the terminals of the components themselves. The grooves are plated with an electrically conductive material, and contain a hole that passes from the upper surface to the bottom surface of the circuit board. When the circuit board is wave soldered, in a conventional manner, solder from the wave soldering process engages the holes, passes through the holes to the upper surface of the circuit board, and then runs along the grooves in the upper surface of the circuit board. Upon solidifying, the solder provides an electrical connection between the components.
Abstract:
To facilitate inspection, the pad metal level of a semiconductor chip (10) includes terminal pads having two different shapes. The terminal pads (18) that are to be functional are patterned in a first shape and the non-functional terminal pads (20) are patterned in an easily distinguishable second shape. Since the final passivation layer is transparent, the two shapes can be distinguished during inspection following the fabrication of solder balls, and rework of defective solder balls on non-functional pads can be avoided.